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Comp.Arch.FPGA | Implementing FIFO in Spartan-II
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Implementing FIFO in Spartan-II - Atif - 2003-08-27 23:46:00
I'm using Spartan-II XC2s50 with platform flash Prom XCF01s. I've to implement a 32x1 FIFO (with 16 bits for data of channel I and 16 for channel Q). I'm thinking to implement it in the Block RAM (Is there any other method which is more efficient than this one in SpartanII?). The dual RAM ports of Spartan-II are configurable to any size from 4Kx1 to 256x16. (In the XAPP173 "Using Block Select Ram+ Memory in Spartan-II" of Xilinx, there is a table1 which don't have port aspect ratios for 32x1) Can I implement FIFO of 32x1 in this BlockRam of Spartan-II? Regards Atif______________________________
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Re: Implementing FIFO in Spartan-II - Jim Wu - 2003-08-28 07:33:00
> I'm thinking to implement it in the Block RAM (Is there any other > method which is more efficient than this one in SpartanII?). > The dual RAM ports of Spartan-II are configurable to any size from > 4Kx1 to 256x16. (In the XAPP173 "Using Block Select Ram+ Memory in > Spartan-II" of Xilinx, there is a table1 which don't have port aspect > ratios for 32x1) > Can I implement FIFO of 32x1 in this BlockRam of Spartan-II? You can use any depth for your FIFO as long as it is below 4K. XAPP175 talks about FIFO implementation in SpartanII. Jim Wu j...@yahoo.com http://www.geocities.com/jimwu88/chips______________________________
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