Hi,

I want to send a video file from a pc to a FPGA (on a XUPV2P development
board) via the PCI interface. On the FPGA the video will be processed by an
algorithm. The result, after processing, will be send back to the pc. I
generated the VHDL-code of the algorithm in Simulink with Xilinx System
Generator (gateway_in and gateway_out are 8 bits wide). I also have the
VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the
algorithm in the PCI-code. 

The resolution of the video is 320x240. The device driver on the pc (Linux)
gives an interrupt at the beginning of every frame. Can someone tell me how
I have to adapt the code of the user application delivered by Xilinx ( code
can be found here : http://www.mediafire.com/?kyygtdm0wlj ) to give the
FPGA a sign to start processing the data and send the result back to the pc
after a frame has been processed? Is there a manner to check how many
bits/bytes/pixels passed by?

Thanks in advance.

Nobody who can help me?


>Hi,
>
>I want to send a video file from a pc to a FPGA (on a XUPV2P development
>board) via the PCI interface. On the FPGA the video will be processed by
an
>algorithm. The result, after processing, will be send back to the pc. I
>generated the VHDL-code of the algorithm in Simulink with Xilinx System
>Generator (gateway_in and gateway_out are 8 bits wide). I also have the
>VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the
>algorithm in the PCI-code. 
>
>The resolution of the video is 320x240. The device driver on the pc
(Linux)
>gives an interrupt at the beginning of every frame. Can someone tell me
how
>I have to adapt the code of the user application delivered by Xilinx (
code
>can be found here : http://www.mediafire.com/?kyygtdm0wlj ) to give the
>FPGA a sign to start processing the data and send the result back to the
pc
>after a frame has been processed? Is there a manner to check how many
>bits/bytes/pixels passed by?
>
>Thanks in advance.
>
>
>
>	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Jan 1, 11:03=A0am, "Ghostboy" <Ghost...@dommel.be> wrote:
> Nobody who can help me?

You're asking for a LOT of work from someone or someone who happens to
actively use a development board that's been discontinued from Xilinx
(you can still purchase it from digilentinc.com) because the Virtex-II
Pro devices are getting old.

Besides, the link in your Dec 14th email is invalid.

Hi,

If someone can just give me directions how to start I would also be happy
:) 
Sorry, this is the new link : http://www.mediafire.com/?h14dvjzn2zn
The file to open is \PCI\pci\vhdl\example\xilinx\xlnx_auto_0.ise 


>On Jan 1, 11:03=A0am, "Ghostboy" <Ghost...@dommel.be> wrote:
>> Nobody who can help me?
>
>You're asking for a LOT of work from someone or someone who happens to
>actively use a development board that's been discontinued from Xilinx
>(you can still purchase it from digilentinc.com) because the Virtex-II
>Pro devices are getting old.
>
>Besides, the link in your Dec 14th email is invalid.
>	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

"Ghostboy" <G...@dommel.be> writes:

>Hi,

>I want to send a video file from a pc to a FPGA (on a XUPV2P development
>board) via the PCI interface. On the FPGA the video will be processed by an
>algorithm. The result, after processing, will be send back to the pc. I
>generated the VHDL-code of the algorithm in Simulink with Xilinx System
>Generator (gateway_in and gateway_out are 8 bits wide). I also have the
>VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the
>algorithm in the PCI-code. 

>The resolution of the video is 320x240. The device driver on the pc (Linux)
>gives an interrupt at the beginning of every frame. Can someone tell me how
>I have to adapt the code of the user application delivered by Xilinx ( code
>can be found here : http://www.mediafire.com/?kyygtdm0wlj ) to give the
>FPGA a sign to start processing the data and send the result back to the pc
>after a frame has been processed? Is there a manner to check how many
>bits/bytes/pixels passed by?

>Thanks in advance.

	With the caveat that I know very little (and therefore this may not be
useful :-)) is it a correct assumtion that the video is coming from another 
PCI card (such as a video capture card)? If so the interrupt being generated
will be to the Linux device driver for the video card (not to the FPGA). It
seems possible to me that the part you are missing isn't FPGA related at all but
a linux device driver that will accept the video data from the source (driven
by the frame interrupt) and send it via the PCI bus to the FPGA card for 
processing. 
	You may find the PCI project (which has a linux device driver) at
http://www.fpga4fun.com/PCI.html of use to you.
	The pci logic analyser code (assuming you can port it to your card of
course) may help with the how many bytes made it across the interface. 

Peter Van Epp

Hi,

The video file is not coming from another PCI card but from the pc. The
code to send and receive data is on top of the PCI driver in Linux. But I
don't know how to let the algorithm (PCI core) on the FPGA know that it can
start processing data and how it can give a signal to the pc that the
processing of a frame is finished. I also want to use the I/O space of the
PCI instead of the memory space but I don't know if that will be fast
enough to process more than 50 frames per second with a resolution of
320x240. 

	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Jan 5, 6:03=A0am, "Ghostboy" <Ghost...@dommel.be> wrote:
> Hi,
>
> The video file is not coming from another PCI card but from the pc. The
> code to send and receive data is on top of the PCI driver in Linux. But I
> don't know how to let the algorithm (PCI core) on the FPGA know that it c=
an
> start processing data and how it can give a signal to the pc that the
> processing of a frame is finished. I also want to use the I/O space of th=
e
> PCI instead of the memory space but I don't know if that will be fast
> enough to process more than 50 frames per second with a resolution of
> 320x240.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com

Why would you want to use I/O space?  The most effective way to
transfer data over simple PCI interfaces (rather than PCI-X or PCIe)
is the Memory Read Multiple transaction to transfer a cache line at a
time rather than a 32-bit word for each transaction.  [I might be
assuming too much up front.  Are you using a master/target PCI core to
perform Direct Memory Accesses (DMAs) to transfer the FPGA-processed
data back to the PC?]

Are you streaming the data or transferring an entire file?

When you design the FPGA logic that hooks up to the PCI core, you have
access to the addresses being written and can maintain a byte count.
When a certain address is written (e.g. a frame of data is complete)
you can begin your processing.  Either your driver or the design of
the system should define the frame size and/or number of frames to
process as well as FPGA memory (or I/O) space that's appropriate for
the writes.  To transfer data back to the PC, the driver should have a
defined DMA space for the master mode of a master/target PCI core and
let the FPGA transfer the data with the memory read multiple
transactions to fill the space and interrupt the processor when
complete.  The interrupt handler on the PC side would then do what it
needs to with the frame and set up the next DMA memory band.

I didn't look at your file in the post above because I don't have a
RAR decompressor on my home machine.

Hi,

I first want to use the I/O space because I think the most simple
implementation.
The possibility to use DMA is not in this core.
If I make a zip file can you open it then? It might be easier to see the
problem.

I'm streaming an entire file by the way.




>Why would you want to use I/O space?  The most effective way to
>transfer data over simple PCI interfaces (rather than PCI-X or PCIe)
>is the Memory Read Multiple transaction to transfer a cache line at a
>time rather than a 32-bit word for each transaction.  [I might be
>assuming too much up front.  Are you using a master/target PCI core to
>perform Direct Memory Accesses (DMAs) to transfer the FPGA-processed
>data back to the PC?]
>
>Are you streaming the data or transferring an entire file?
>
>When you design the FPGA logic that hooks up to the PCI core, you have
>access to the addresses being written and can maintain a byte count.
>When a certain address is written (e.g. a frame of data is complete)
>you can begin your processing.  Either your driver or the design of
>the system should define the frame size and/or number of frames to
>process as well as FPGA memory (or I/O) space that's appropriate for
>the writes.  To transfer data back to the PC, the driver should have a
>defined DMA space for the master mode of a master/target PCI core and
>let the FPGA transfer the data with the memory read multiple
>transactions to fill the space and interrupt the processor when
>complete.  The interrupt handler on the PC side would then do what it
>needs to with the frame and set up the next DMA memory band.
>
>I didn't look at your file in the post above because I don't have a
>RAR decompressor on my home machine.
>	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Jan 5, 8:06=A0am, "Ghostboy" <Ghost...@dommel.be> wrote:
> Hi,
>
> I first want to use the I/O space because I think the most simple
> implementation.
> The possibility to use DMA is not in this core.
> If I make a zip file can you open it then? It might be easier to see the
> problem.
>
> I'm streaming an entire file by the way.
>
What work have you done or *can* you do?  You've used system generator
and other high level tools.  Are you familiar with low level FPGA
design?  Are you looking to get someone to do this low level design
work for you?

Is your need on the PC driver for the XUPV2P such that you need
software help?

Having a zip file I can actually look at won't help me to help you if
I don't know what you need.

I've suggested on the FPGA side that you use the writes to the FPGA
(quantity and/or addresses) to know when a fram of data is available
and that you use a PCI interrupt to tell the PC when the FPGA is
done.  You specifically asked for those.

What more are you asking for?

Hi,

I must admit that I'm searching for the VHDL-code that combines the PCI
core and the algorithm.


>On Jan 5, 8:06=A0am, "Ghostboy" <Ghost...@dommel.be> wrote:
>> Hi,
>>
>> I first want to use the I/O space because I think the most simple
>> implementation.
>> The possibility to use DMA is not in this core.
>> If I make a zip file can you open it then? It might be easier to see
the
>> problem.
>>
>> I'm streaming an entire file by the way.
>>
>What work have you done or *can* you do?  You've used system generator
>and other high level tools.  Are you familiar with low level FPGA
>design?  Are you looking to get someone to do this low level design
>work for you?
>
>Is your need on the PC driver for the XUPV2P such that you need
>software help?
>
>Having a zip file I can actually look at won't help me to help you if
>I don't know what you need.
>
>I've suggested on the FPGA side that you use the writes to the FPGA
>(quantity and/or addresses) to know when a fram of data is available
>and that you use a PCI interrupt to tell the PC when the FPGA is
>done.  You specifically asked for those.
>
>What more are you asking for?
>	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com