I hope my plea will not be seen as usual
"please help me" request. I
do my (home)work, I try hard but sometimes there come up problems that
seem very hard to solve, with the current problem, well if there is no
solution to that, then I wonder how come it has been ever been
possible to use Xilinx FIFO's with problem at all? So the problem:

Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY
flags present.

signals at input correct, as expected (checked with ChipScope)
signals at output:
- double value
- missing 1, 2 or 3 values
- FIFO will read out random number of OLD entries, this could be 4
values, or 50% of the FIFO old values

I can select BRAM or FIFO16 implementation in Coregen, it doesnt
change the problem

Virtex-4, ISE 10.1SP3

Please help me, if anyone has some good suggestion (except use Altera
advice), I am getting really desperate. To the extent that when i
friend called my yesterday, then after my "hello", his first response
was: "Are you dead?". I had to explain that i am not.

Antti

> Virtex-4, FIFOs

I thought I read there was a bug in those...

On Dec 21, 11:40=A0am, Jon Beniston
<j...@beniston.com> wrote:
> > Virtex-4, FIFOs
>
> I thought I read there was a bug in those...

Well there is a bug in the V4 FIFO16 hard-fifo, but Coregen says that
it DOES APPLY PATCH to fix it.

So I assumed that the FIFO's generated by Coregen do actually work,
but it seems i was wrong :(

Antti

Why dont you just write your own fifo? It
shouldnt take that long and atleast you would know it was 100% ok.

Jon	   
					
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On Dec 21, 12:07=A0pm, "maxascent"
<maxasc...@yahoo.co.uk> wrote:
> Why dont you just write your own fifo? It shouldnt take that long and at
> least you would know it was 100% ok.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0

Yeah, that advice I have myself ready :) well, I would most likely not
use FIFO
but make dual port RAM instead. Thing is that the system works, the
firmware
works, except that "small Xilinx FIFO problem" .. so if there is at
all chance
to FIX Xilinx FIFO and to make it WORK then it would made the system
work
without the need of rewriting HDL or C code

Antti

Well once you have written and tested your own
fifo then you would have itfor any other project. It seems like you have wasted a lot of time alreadytrying to fix the Xilinx version so I dont see that you have anything toloose by creating your own.

Jon	   
					
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Antti wrote:
> 
> Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY
> flags present.
> 
> signals at input correct, as expected (checked with ChipScope)
> signals at output:
> - double value
> - missing 1, 2 or 3 values
> - FIFO will read out random number of OLD entries, this could be 4
> values, or 50% of the FIFO old values
> 
I know you will have read this.


Can you think of any reason why the Xilinx work-around wouldn't work 
because of your specific implementation? It seems to have different 
work-arounds depending on whether the read clock is faster or slower 
than the write clock. Do your clocks change frequency?

Are you sure your clocks don't have any glitches? The reset also? 
Power's OK? Is your office made of Cobalt 60?

HTH., Syms.

On Dec 21, 12:56=A0pm, Symon
<symon_bre...@hotmail.com> wrote:
> Antti wrote:
>
> > Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY
> > flags present.
>
> > signals at input correct, as expected (checked with ChipScope)
> > signals at output:
> > - double value
> > - missing 1, 2 or 3 values
> > - FIFO will read out random number of OLD entries, this could be 4
> > values, or 50% of the FIFO old values
>
> I know you will have read this.
>
> Can you think of any reason why the Xilinx work-around wouldn't work
> because of your specific implementation? It seems to have different
> work-arounds depending on whether the read clock is faster or slower
> than the write clock. Do your clocks change frequency?
>
> Are you sure your clocks don't have any glitches? The reset also?
> Power's OK? Is your office made of Cobalt 60?
>
> HTH., Syms.

1) I entered the clock figures in FIFO16 implementationm, but the
error also happens with BRAM based FIFO that do not need workarounds
2) Clocks DO NOT CHANGE ever, one is MGT recovered clock 125MHz write,
one is PLB clock 62.5MHz read
3) Power OK? Well the problem happens at 2 different sites, hm yes it
could be still be power problem

4) My office is not of Cobalt 60, ... and its cold here too

Antti

On Dec 21, 12:32=A0pm, "maxascent"
<maxasc...@yahoo.co.uk> wrote:
> Well once you have written and tested your own fifo then you would have i=
t
> for any other project. It seems like you have wasted a lot of time alread=
y
> trying to fix the Xilinx version so I dont see that you have anything to
> loose by creating your own.
>
> Jon =A0 =A0 =A0 =A0
>
If you REALLY need todo something else, when your time is at absolute
premium
And if the system working (except occasional errors about 2 of fiber
packets are corrupt)
Then you do not go replacing Xilinx validated FIFO solutions with your
own, if there are other options.

If 2 completly different FIFO implementations both have same error?
you think 3rd one would instantly work? Could be, yes.

Antti

>On Dec 21, 12:32=A0pm, "maxascent"
<maxasc...@yahoo.co.uk> wrote:
>> Well once you have written and tested your own fifo then you would havei=
>t
>> for any other project. It seems like you have wasted a lot of timealread=
>y
>> trying to fix the Xilinx version so I dont see that you have anythingto
>> loose by creating your own.
>>
>> Jon =A0 =A0 =A0 =A0
>>
>If you REALLY need todo something else, when your time is at absolute
>premium
>And if the system working (except occasional errors about 2 of fiber
>packets are corrupt)
>Then you do not go replacing Xilinx validated FIFO solutions with your
>own, if there are other options.
>
>If 2 completly different FIFO implementations both have same error?
>you think 3rd one would instantly work? Could be, yes.
>
>Antti
>
>

In my opinion people tend to use coregen far too often. Looking throughsome of Xilinx code it is awfull. I went down the route of writing my ownfifos not because I had a problem with Xilinx fifos but because I believe afifo written by myself is a lot more flexible and simulates faster than theXilinx version. I also know to as good a degree as I can test that it willwork 100%.
I dont really think you can say that their fifos have been validated 100%if they have to release patches for them.

Jon	   
					
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