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i have a cypress fx2lp usb2 that emulates an ACE hdl player and outputs theJtag directly to an XCF32P and an SX55. there are a couple of issues i am still not sure about though, 1- on a TDO check, the ace file gives me the output data for TDI, a mask,and an expected return value. The SX55 and XCF32P have a combined TDO buffer of 26 bits, so from whati gather i dont get the data back out for 26 clock cycles, does this meanthat i should just continue clocking with no new instructions or data untili get all the data back or do i continue feeding in new instructions andjust wait the 26 clocks like that? 2- what is the maximum TDO length for an ACE file? i have the FX2LP packedfull and can barely fit in another byte of storage, if i have to hold 100+bytes in ram to check later im kind of screwed... 3- the XAPP424 talks about having to clock on the runtest instruction if itis configuring an FPGA, the FX2LP link is not exactly fast enough tocontinuously feed data through so the clock is sometimes just held high orlow for slightly longer periods on different instructions as im justbit-banging it. should i slow it all down so i have a continuous clockperiod or does it not matter as only the rising edge and minimum clock highperiods are the only important parts?
I realized i was reading the TDO instructions incorrectly from the XAPP424and so i only need to store 26 bits or mask and 26 of expected TDO and 26bits of received TDO, i thought it was <opcode><all TDI data><all TDOexpected><all TDO mask>, but it looks like it is broken into bytes ofeach... <0x04><numbits> <TDI byte> <TDO exp byte> <TDO mask byte> <TDI byte> <TDOexp> ... unfortunately it takes about an hour to run this programming procedure asthe ace file is about 40MB which has to go down endpoint0 and i have anerror check so its 2 transfers for every 32bytes. i will update if itworked... --------------------------------------- This message was sent using the comp.arch.fpga web interface onhttp://www.FPGARelated.com
still not programming.... --------------------------------------- This message was sent using the comp.arch.fpga web interface onhttp://www.FPGARelated.com______________________________