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Comp.Arch.FPGA | RTL View of synthezied code

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

RTL View of synthezied code - jozamm - 2009-12-31 02:28:00

Hi all,

I implemented a small statemachine with 2 states, State A triggers
counter A, when counter A reaches 255 the state machine jumps to state
B which triggers counter B, when counter B reaches 255 the state
machine goes to state A again. This repeats forever.

The counter is implemented as a component and the top module
instantiates two of them. The code is in VHDL and I am using Xilinx
ISE 11.4 When I viewed the RTL schematic, one counter is connected to
the rest of the state machine and the counter is floating with no
connections. However when i wrote a testbench and simulated it the
result is correct.

Can please someone give me an explanation?

Thanks and Happy New Year,

Regards,

Joseph



Re: RTL View of synthezied code - jt_eaton - 2009-12-31 11:41:00

>Hi all,
>
>I implemented a small statemachine with 2 states, State A triggers
>counter A, when counter A reaches 255 the state machine jumps to state
>B which triggers counter B, when counter B reaches 255 the state
>machine goes to state A again. This repeats forever.
>
>The counter is implemented as a component and the top module
>instantiates two of them. The code is in VHDL and I am using Xilinx
>ISE 11.4 When I viewed the RTL schematic, one counter is connected to
>the rest of the state machine and the counter is floating with no
>connections. However when i wrote a testbench and simulated it the
>result is correct.
>
>Can please someone give me an explanation?
>
>Thanks and Happy New Year,
>
>Regards,
>
>Joseph

It probably determined that the two counters are never used at the sametime and could use one to do both tasks. Try changing the time outs tonon-matching values and see how that affects the outcome.



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