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Comp.Arch.FPGA | E1 clock problem with Spartan3e...
There are 8 messages in this thread.
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E1 clock problem with Spartan3e... - Morppheu - 2010-01-11 11:22:00
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? Today I have a process to detect if E1 F0 signals is present. If its present, I switch from internal clock to E1 clock : clk_res <= clk_int when E1_present = 0 else clk_e1; I know its a very bad design technique, but its an old code from another guy and I am looking to make the things right. What is the best way to interface with E1? Can someone help me? Thanks!
Re: E1 clock problem with Spartan3e... - Nico Coesel - 2010-01-11 15:08:00
Morppheu <j...@gmail.com> wrote: >Hey guys... > >I need a little help with my E1 interface. >I have an internal clock and the E1 clock. When E1 chip (MT9076B) is >present I use the E1 clock + E1 F0 signals, else I use the internal >clock. Why use the internal clock? Isn't the MT9076 free running when it doesn't see a line-sync? >I know its a very bad design technique, but its an old code from >another guy and I am looking to make the things right. >What is the best way to interface with E1? Many years ago I did a design using the MT9075. I let its internal PLL deal with the E1 clock. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
Re: E1 clock problem with Spartan3e... - Morppheu - 2010-01-12 09:00:00
> Why use the internal clock? Isn't the MT9076
free running when it
> doesn't see a line-sync?
Yes, the MT goes free running when its not sinced.
But the MT9076 is a module on my hardware. I can mount the backplane
with or without the MT9076 chip.
That is the point, what to do when I have the E1 module installed. How
to interface with it.
My FPGA is an Spartan 3e S100 (almost 100% full):
Logic Utilization:
Total Number Slice Registers: 737 out of 1,920 38%
Number used as Flip Flops: 731
Number used as Latches: 6
Number of 4 input LUTs: 956 out of 1,920 49%
Logic Distribution:
Number of occupied Slices: 959 out of
960 99%
Number of Slices containing only related logic: 959 out of
959 100%
Number of Slices containing unrelated logic: 0 out of
959 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 1,910 out of 1,920 99%
Number used as logic: 956
Number used as a route-thru: 181
Number used for Dual Port RAMs: 768
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 5
Number of bonded IOBs: 93 out of 108 86%
IOB Flip Flops: 19
Number of Block RAMs: 4 out of 4 100%
Number of GCLKs: 9 out of 24 37%
Number of DCMs: 2 out of 2 100%
Another thing. How to reduce the area usage??
Thanks!
Re: E1 clock problem with Spartan3e... - Nico Coesel - 2010-01-12 13:18:00
Morppheu <j...@gmail.com> wrote: >> Why use the internal clock? Isn't the MT9076 free running when it >> doesn't see a line-sync? > >Yes, the MT goes free running when its not sinced. That is not a problem. Just use that clock always. >But the MT9076 is a module on my hardware. I can mount the backplane >with or without the MT9076 chip. I guess the logic is idle when the module is not mounted. Pulling the clock down or up to have a defined logic level should do it. >That is the point, what to do when I have the E1 module installed. How >to interface with it. >My FPGA is an Spartan 3e S100 (almost 100% full): > >Logic Utilization: > Total Number Slice Registers: 737 out of 1,920 38% > Number used as Flip Flops: 731 > Number used as Latches: 6 > Number of 4 input LUTs: 956 out of 1,920 49% >Logic Distribution: > Number of occupied Slices: 959 out of >960 99% > Number of Slices containing only related logic: 959 out of >959 100% > Number of Slices containing unrelated logic: 0 out of >959 0% > *See NOTES below for an explanation of the effects of unrelated >logic >Total Number of 4 input LUTs: 1,910 out of 1,920 99% > Number used as logic: 956 > Number used as a route-thru: 181 > Number used for Dual Port RAMs: 768 > (Two LUTs used per Dual Port RAM) > Number used as Shift registers: 5 > Number of bonded IOBs: 93 out of 108 86% > IOB Flip Flops: 19 > Number of Block RAMs: 4 out of 4 100% > Number of GCLKs: 9 out of 24 37% > Number of DCMs: 2 out of 2 100% > >Another thing. How to reduce the area usage?? Almost half the LUTs are used as dual port rams. Perhaps an inefficient FIFO for audio/D channel? I'd use boundary crossing registers instead of a FIFO. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------______________________________
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Re: E1 clock problem with Spartan3e... - rickman - 2010-01-13 10:35:00
I'm not sure where this thread started, I don't see a message before Nico's post Jan 11. Did you post your code? Your design is using about 10% of the LUTs as routing, which does tend to happen when your LUT usage rises using up much of the routing resources. The main offender that I can see is the use of almost 50% of the LUTs as DP RAM. I am guessing that these are being used for FIFO buffers. Can you reduce the number of LUTs used for buffering or are they all required? As to the clocking issue, I don't know what the problem is exactly. Why can't you use the E1 clock? What pin is the E1 clock connected to on the S3 part? I would hope it is connected to a DCM or at least a clock input. It is hard to suggest much more without more insight into what your design is doing. Rick On Jan 12, 9:00=A0am, Morppheu <jdemam...@gmail.com> wrote: > > Why use the internal clock? Isn't the MT9076 free running when it > > doesn't see a line-sync? > > Yes, the MT goes free running when its not sinced. > But the MT9076 is a module on my hardware. I can mount the backplane > with or without the MT9076 chip. > That is the point, what to do when I have the E1 module installed. How > to interface with it. > My FPGA is an Spartan 3e S100 (almost 100% full): > > Logic Utilization: > =A0 Total Number Slice Registers: =A0 =A0 =A0 737 out of =A0 1,920 =A0 38= % > =A0 =A0 Number used as Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 73= 1 > =A0 =A0 Number used as Latches: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A06 > =A0 Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 956 out of =A0 1,920 = =A0 49% > Logic Distribution: > =A0 Number of occupied Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0959 out of > 960 =A0 99% > =A0 =A0 Number of Slices containing only related logic: =A0 =A0 959 out o= f > 959 =A0100% > =A0 =A0 Number of Slices containing unrelated logic: =A0 =A0 =A0 =A0 =A00= out of > 959 =A0 =A00% > =A0 =A0 =A0 *See NOTES below for an explanation of the effects of unrelat= ed > logic > Total Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A01,910 out of =A0 1,920 = =A0 99% > =A0 Number used as logic: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0956 > =A0 Number used as a route-thru: =A0 =A0 =A0 =A0 181 > =A0 Number used for Dual Port RAMs: =A0 =A0 =A0768 > =A0 =A0 (Two LUTs used per Dual Port RAM) > =A0 Number used as Shift registers: =A0 =A0 =A0 =A05 > =A0 Number of bonded IOBs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 93 out of =A0 =A0 = 108 =A0 86% > =A0 =A0 IOB Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A019 > =A0 Number of Block RAMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A04 out of =A0 =A0= =A0 4 =A0100% > =A0 Number of GCLKs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 9 out of =A0= =A0 =A024 =A0 37% > =A0 Number of DCMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A02 out of = =A0 =A0 =A0 2 =A0100% > > Another thing. How to reduce the area usage?? > > Thanks!______________________________
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Re: E1 clock problem with Spartan3e... - Morppheu - 2010-01-28 11:59:00
On Jan 13, 1:35=A0pm, rickman <gnu...@gmail.com> wrote: > I'm not sure where this thread started, I don't see a message before > Nico's post Jan 11. =A0Did you post your code? > > Your design is using about 10% of the LUTs as routing, which does tend > to happen when your LUT usage rises using up much of the routing > resources. =A0The main offender that I can see is the use of almost 50% > of the LUTs as DP RAM. =A0I am guessing that these are being used for > FIFO buffers. =A0Can you reduce the number of LUTs used for buffering or > are they all required? > > As to the clocking issue, I don't know what the problem is exactly. > Why can't you use the E1 clock? =A0What pin is the E1 clock connected to > on the S3 part? =A0I would hope it is connected to a DCM or at least a > clock input. > > It is hard to suggest much more without more insight into what your > design is doing. > > Rick > > On Jan 12, 9:00=A0am, Morppheu <jdemam...@gmail.com> wrote:> > Why use th= e internal clock? Isn't the MT9076 free running when it > > > doesn't see a line-sync? > > > Yes, the MT goes free running when its not sinced. > > But the MT9076 is a module on my hardware. I can mount the backplane > > with or without the MT9076 chip. > > That is the point, what to do when I have the E1 module installed. How > > to interface with it. > > My FPGA is an Spartan 3e S100 (almost 100% full): > > > Logic Utilization: > > =A0 Total Number Slice Registers: =A0 =A0 =A0 737 out of =A0 1,920 =A0 = 38% > > =A0 =A0 Number used as Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = 731 > > =A0 =A0 Number used as Latches: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A06 > > =A0 Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 956 out of =A0 1,92= 0 =A0 49% > > Logic Distribution: > > =A0 Number of occupied Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0959 out of > > 960 =A0 99% > > =A0 =A0 Number of Slices containing only related logic: =A0 =A0 959 out= of > > 959 =A0100% > > =A0 =A0 Number of Slices containing unrelated logic: =A0 =A0 =A0 =A0 = =A00 out of > > 959 =A0 =A00% > > =A0 =A0 =A0 *See NOTES below for an explanation of the effects of unrel= ated > > logic > > Total Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A01,910 out of =A0 1,920= =A0 99% > > =A0 Number used as logic: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0956 > > =A0 Number used as a route-thru: =A0 =A0 =A0 =A0 181 > > =A0 Number used for Dual Port RAMs: =A0 =A0 =A0768 > > =A0 =A0 (Two LUTs used per Dual Port RAM) > > =A0 Number used as Shift registers: =A0 =A0 =A0 =A05 > > =A0 Number of bonded IOBs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 93 out of =A0 = =A0 108 =A0 86% > > =A0 =A0 IOB Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A019 > > =A0 Number of Block RAMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A04 out of =A0 = =A0 =A0 4 =A0100% > > =A0 Number of GCLKs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 9 out of = =A0 =A0 =A024 =A0 37% > > =A0 Number of DCMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A02 out of= =A0 =A0 =A0 2 =A0100% > > > Another thing. How to reduce the area usage?? > > > Thanks! Hey guys! Thanks for your reply. =3D) I will explain my problem. I have a internal clock of 16.384MHz (50ppm) and a E1 interface (MT9076B). The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame sync signal, active low). When the E1 is installed (MT9076 chip is soldered at motherboard), I use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I use to send the E1 data to MT9076, aligned with F0 signal. What I want to do is use only the internal 2.048MHz (generate from 16.384MHz clock, with DCM) and interface with E1 through a FIFO. Here is the problem. Internal and external clock are different, so the FIFO will go underflow or overflow... What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 goes free running I will have problem anyway. Waiting suggestions.. =3D) Thanks!______________________________
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Re: E1 clock problem with Spartan3e... - RCIngham - 2010-01-29 06:18:00
[older stuff elided] >I will explain my problem. >I have a internal clock of 16.384MHz (50ppm) and a E1 interface >(MT9076B). >The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame >sync signal, active low). >When the E1 is installed (MT9076 chip is soldered at motherboard), I >use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e >S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I >use to send the E1 data to MT9076, aligned with F0 signal. >What I want to do is use only the internal 2.048MHz (generate from >16.384MHz clock, with DCM) and interface with E1 through a FIFO. >Here is the problem. Internal and external clock are different, so the >FIFO will go underflow or overflow... >What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 >goes free running I will have problem anyway. > >Waiting suggestions.. =3D) > >Thanks! > Ignoring the FPGA implementation issues and concentrating on the systemdesign for a moment: What you want is a local Nx2048kHz clock, which can be slaved to anexternal 2048kHz clock when it is present (probably by a PLL), butfree-runs at the correct nominal frequency when absent. This was quite acommon requirement for telecomms equipment about 20 years ago. Thus when there is valid E1 data, none is lost. How to implement this using the inferior clock resources of the Spartanseries of FPGAs is a rather harder question, which is left to others... Cheers, Robert --------------------------------------- Posted through http://www.FPGARelated.com
Re: E1 clock problem with Spartan3e... - rickman - 2010-01-29 15:19:00
On Jan 28, 11:59=A0am, Morppheu <jdemam...@gmail.com> wrote: > On Jan 13, 1:35=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I'm not sure where this thread started, I don't see a message before > > Nico's post Jan 11. =A0Did you post your code? > > > Your design is using about 10% of the LUTs as routing, which does tend > > to happen when your LUT usage rises using up much of the routing > > resources. =A0The main offender that I can see is the use of almost 50% > > of the LUTs as DP RAM. =A0I am guessing that these are being used for > > FIFO buffers. =A0Can you reduce the number of LUTs used for buffering o= r > > are they all required? > > > As to the clocking issue, I don't know what the problem is exactly. > > Why can't you use the E1 clock? =A0What pin is the E1 clock connected t= o > > on the S3 part? =A0I would hope it is connected to a DCM or at least a > > clock input. > > > It is hard to suggest much more without more insight into what your > > design is doing. > > > Rick > > > On Jan 12, 9:00=A0am, Morppheu <jdemam...@gmail.com> wrote:> > Why use = the internal clock? Isn't the MT9076 free running when it > > > > doesn't see a line-sync? > > > > Yes, the MT goes free running when its not sinced. > > > But the MT9076 is a module on my hardware. I can mount the backplane > > > with or without the MT9076 chip. > > > That is the point, what to do when I have the E1 module installed. Ho= w > > > to interface with it. > > > My FPGA is an Spartan 3e S100 (almost 100% full): > > > > Logic Utilization: > > > =A0 Total Number Slice Registers: =A0 =A0 =A0 737 out of =A0 1,920 = =A0 38% > > > =A0 =A0 Number used as Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 731 > > > =A0 =A0 Number used as Latches: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A06 > > > =A0 Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 956 out of =A0 1,= 920 =A0 49% > > > Logic Distribution: > > > =A0 Number of occupied Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0959 out of > > > 960 =A0 99% > > > =A0 =A0 Number of Slices containing only related logic: =A0 =A0 959 o= ut of > > > 959 =A0100% > > > =A0 =A0 Number of Slices containing unrelated logic: =A0 =A0 =A0 =A0 = =A00 out of > > > 959 =A0 =A00% > > > =A0 =A0 =A0 *See NOTES below for an explanation of the effects of unr= elated > > > logic > > > Total Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A01,910 out of =A0 1,9= 20 =A0 99% > > > =A0 Number used as logic: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0956 > > > =A0 Number used as a route-thru: =A0 =A0 =A0 =A0 181 > > > =A0 Number used for Dual Port RAMs: =A0 =A0 =A0768 > > > =A0 =A0 (Two LUTs used per Dual Port RAM) > > > =A0 Number used as Shift registers: =A0 =A0 =A0 =A05 > > > =A0 Number of bonded IOBs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 93 out of =A0 = =A0 108 =A0 86% > > > =A0 =A0 IOB Flip Flops: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A019 > > > =A0 Number of Block RAMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A04 out of =A0= =A0 =A0 4 =A0100% > > > =A0 Number of GCLKs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 9 out of= =A0 =A0 =A024 =A0 37% > > > =A0 Number of DCMs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A02 out = of =A0 =A0 =A0 2 =A0100% > > > > Another thing. How to reduce the area usage?? > > > > Thanks! > > Hey guys! > Thanks for your reply. =3D) > I will explain my problem. > I have a internal clock of 16.384MHz (50ppm) and a E1 interface > (MT9076B). > The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame > sync signal, active low). > When the E1 is installed (MT9076 chip is soldered at motherboard), I > use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e > S100 sucks) I use to generate a 2MHz clock from E1 clock. This clock I > use to send the E1 data to MT9076, aligned with F0 signal. > What I want to do is use only the internal 2.048MHz (generate from > 16.384MHz clock, with DCM) and interface with E1 through a FIFO. > Here is the problem. Internal and external clock are different, so the > FIFO will go underflow or overflow... > What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 > goes free running I will have problem anyway. > > Waiting suggestions.. =3D) > > Thanks! I guess I don't understand how things are connected. You seem to have three clocks in the system and I don't know when (or why) you want to use what clock. I understand that the E1 clock at 2.048 MHz is used to clock data from the interface. I think you want to sync the internal 16.384 MHz clock to the E1 so you can process data faster than the 2.048 MHz clock allows. But what is the clock from the MT9076 chip used for? If the MT clock is used to clock data when the E1 clock is not present, you will need to mux the two clocks (E1 and MT) before using them to sync to the internal clock. Does that do the job you are looking for? Rick