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Comp.Arch.FPGA | Timing errors in Post route simulation in modelsim
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Timing errors in Post route simulation in modelsim - gentel - 2010-01-12 07:37:00
Hi, when i do post route simulation i get a bunch of error similar to thefollowing ** Error:F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps,520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_4 # ** Error:F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps,520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_1 # ** Error:F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps,520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_2 # ** Error:F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps,520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram_addr_3 who can tell me how to correct these errors?? --------------------------------------- This message was sent using the comp.arch.fpga web interface onhttp://www.FPGARelated.com
