Sir,
       I am designing DLL using DCM on VERTEX4. But I am not gwtting
output for clk2x, clk2x180 I am giving my code below. I am not able to
find  whetre is the fault. I have written this code in architecture
code, I didn't use coreIP where generates .xaw file .
I tried that too but not got expected result ?


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 library UNISIM;
 use UNISIM.VComponents.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_dll is
    Port ( sys_clk,reset_in : in  STD_LOGIC;
 
fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out
STD_LOGIC);
end clk_dll;

architecture Behavioral of clk_dll is
signal
clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_logic;
component IBUFG
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;

Component BUFG
 port (
   O : out std_logic;
   I : in std_logic );
end component;

component DCM_BASE
 port (
   CLK0 : out std_logic;
   CLK90 : out std_logic;
   CLK180 : out std_logic;
   CLK270 : out std_logic;
   CLK2X : out std_logic;
   CLK2X180 : out std_logic;
   CLKDV : out std_logic;
   CLKFX : out std_logic;
   CLKFX180 : out std_logic;
   LOCKED : out std_logic;
   CLKIN : in std_logic;
   CLKFB : in std_logic;
   RST : in std_logic );
end component;


begin
ibuf0:ibufg port map(i=>sys_clk,o=>clk0a);
buf1: bufg port map (i=> clk0_buf, o=> clk_fb_in);




dll: DCM_BASE port map (CLKIN => clk0a, CLKFB => Clk_FB_in, RST =>
Reset_in, CLK0 => Clk0_buf,
	       		CLK90 => clk90_buf, CLK180 => clk180_buf, CLK270 =>
clk270_buf, CLK2X => clk2x_buf, CLK2X180 => OPEN,
			CLKDV => open, CLKFX => OPEN, CLKFX180 => OPEN, LOCKED =>
locked_out);

fpga_clk<=clk_fb_in;
buf2:bufg port map(i=>clk90_buf,o=>clk90_out);
buf3:bufg port map(i=>clk180_buf,o=>clk180_out);
buf4:bufg port map(i=>clk270_buf,o=>clk270_out);
buf5:bufg port map(i=>clk2x_buf,o=>fpga_clk2x);
end Behavioral;

On Jan 18, 1:15=A0am, abhishek kumar
<abkv...@gmail.com> wrote:
> Sir,
> =A0 =A0 =A0 =A0I am designing DLL using DCM on VERTEX4. But I am not gwtt=
ing
> output for clk2x, clk2x180 I am giving my code below. I am not able to
> find =A0whetre is the fault. I have written this code in architecture
> code, I didn't use coreIP where generates .xaw file .
> I tried that too but not got expected result ?
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> =A0library UNISIM;
> =A0use UNISIM.VComponents.all;
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity clk_dll is
> =A0 =A0 Port ( sys_clk,reset_in : in =A0STD_LOGIC;
>
> fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out
> STD_LOGIC);
> end clk_dll;
>
> architecture Behavioral of clk_dll is
> signal
> clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_l=
ogic;
> component IBUFG
> =A0port (
> =A0 =A0O : out std_logic;
> =A0 =A0I : in std_logic
> =A0);
> end component;
>
> Component BUFG
> =A0port (
> =A0 =A0O : out std_logic;
> =A0 =A0I : in std_logic );
> end component;
>
> component DCM_BASE
> =A0port (
> =A0 =A0CLK0 : out std_logic;
> =A0 =A0CLK90 : out std_logic;
> =A0 =A0CLK180 : out std_logic;
> =A0 =A0CLK270 : out std_logic;
> =A0 =A0CLK2X : out std_logic;
> =A0 =A0CLK2X180 : out std_logic;
> =A0 =A0CLKDV : out std_logic;
> =A0 =A0CLKFX : out std_logic;
> =A0 =A0CLKFX180 : out std_logic;
> =A0 =A0LOCKED : out std_logic;
> =A0 =A0CLKIN : in std_logic;
> =A0 =A0CLKFB : in std_logic;
> =A0 =A0RST : in std_logic );
> end component;
>
> begin
> ibuf0:ibufg port map(i=3D>sys_clk,o=3D>clk0a);
> buf1: bufg port map (i=3D> clk0_buf, o=3D> clk_fb_in);
>
> dll: DCM_BASE port map (CLKIN =3D> clk0a, CLKFB =3D> Clk_FB_in, RST =3D>
> Reset_in, CLK0 =3D> Clk0_buf,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90 =3D> clk90_buf, CLK=
180 =3D> clk180_buf, CLK270 =3D>
> clk270_buf, CLK2X =3D> clk2x_buf, CLK2X180 =3D> OPEN,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV =3D> open, CLKFX =
=3D> OPEN, CLKFX180 =3D> OPEN, LOCKED =3D>
> locked_out);
>
> fpga_clk<=3Dclk_fb_in;
> buf2:bufg port map(i=3D>clk90_buf,o=3D>clk90_out);
> buf3:bufg port map(i=3D>clk180_buf,o=3D>clk180_out);
> buf4:bufg port map(i=3D>clk270_buf,o=3D>clk270_out);
> buf5:bufg port map(i=3D>clk2x_buf,o=3D>fpga_clk2x);
> end Behavioral;

There are a number of generics required to set up the DCM
in the correct operating mode, not the least of which is
DLL_FREQUENCY_MODE, which must be "LOW" in order to get
the 2x outputs.  Look in the Virtex-4 Libraries Guide for
HDL Designs, available from the ISE help menu under
"Software Manuals."  There are instantiation templates
in the manual which should help.  Also refer to your
Virtex 4 data sheet to make sure your part is spec'd
to work in low frequency mode with your clock input
frequency.

HTH,
Gabor