Hello, 
I am implementing a processor design on the virtex 2 chip. The Design wasdone using verilog with Xilinx 10.1 and modelsim. I have a compiler of thedesign. 

My question is:is there a way to integrate the compiler output with theFPGA using modelsim simulator without actually programming the fpga. I amusing a windows system and the complier is C based.

Thank you
Akshay

	   
					
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On Mon, 18 Jan 2010 18:07:01 -0600,
"akshayvreddy" <a...@gmail.com>
wrote:

>Hello, 
>I am implementing a processor design on the virtex 2 chip. The Design was
>done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the
>design. 
>
>My question is:is there a way to integrate the compiler output with the
>FPGA using modelsim simulator without actually programming the fpga. I am
>using a windows system and the complier is C based.
>
>Thank you
>Akshay

Yes.

Where is the program memory for the processor?

If external memory, you can modify a memory model to load (and save) its
contents from a file. I have done this by adding extra "load", "save"
and
"filename" ports to a memory model I originally downloaded from a memory
manufacturer (Cypress), and driving them from the testbench.

Actually loading an object code file is then a simple matter of programming.

If you are using BRAMs, you can instantiate them and translate your object code
into their INIT_nn generics. 

But it is much better and easier to infer a ROM as a constant array, initialised
by a function (which is called during elaboration). That function could read
your object file into the ROM. Or you could write another program to translate
the object format into a VHDL package containing your constant array.

(I don't know Verilog but I expect it can do these things too)

- Brian

On Jan 19, 7:10=A0am, Brian Drummond
<brian_drumm...@btconnect.com>
wrote:
> On Mon, 18 Jan 2010 18:07:01 -0600, "akshayvreddy"
<akshayvre...@gmail.co=
m>
> wrote:
>
> >Hello,
> >I am implementing a processor design on the virtex 2 chip. The Design wa=
s
> >done using verilog with Xilinx 10.1 and modelsim. I have a compiler of t=
he
> >design.
>
> >My question is:is there a way to integrate the compiler output with the
> >FPGA using modelsim simulator without actually programming the fpga. I a=
m
> >using a windows system and the complier is C based.
>
> >Thank you
> >Akshay
>
> Yes.
>
> Where is the program memory for the processor?
>
> If external memory, you can modify a memory model to load (and save) its
> contents from a file. I have done this by adding extra "load",
"save" and
> "filename" ports to a memory model I originally downloaded from a memory
> manufacturer (Cypress), and driving them from the testbench.
>
> Actually loading an object code file is then a simple matter of programmi=
ng.
>
> If you are using BRAMs, you can instantiate them and translate your objec=
t code
> into their INIT_nn generics.
>
> But it is much better and easier to infer a ROM as a constant array, init=
ialised
> by a function (which is called during elaboration). That function could r=
ead
> your object file into the ROM. Or you could write another program to tran=
slate
> the object format into a VHDL package containing your constant array.
>
> (I don't know Verilog but I expect it can do these things too)
>
> - Brian

For Verilog, you can generate ASCII hex files for initialization using
$readmemh.  If you place the $readmemh in an initial block in the
module where the memory is inferred, it will also work for synthesis,
at least in XST 10.1

On Tue, 19 Jan 2010 06:27:03 -0800 (PST), Gabor
wrote:

>For Verilog, you can generate ASCII hex files for initialization using
>$readmemh.  If you place the $readmemh in an initial block in the
>module where the memory is inferred, it will also work for synthesis,
>at least in XST 10.1

If you're a VHDL user, you can get a simulation-only 
VHDL implementation of $readmem (reads exactly the 
same input text files) here:

  http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip

One day, when there's less work to do, I intend to add a
few more file formats to its capabilities - but for now it
only knows how to mimic Verilog $readmemb/h.
-- 
Jonathan Bromley

Jonathan Bromley wrote:
>   http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip
> One day, when there's less work to do, I intend to add a
> few more file formats to its capabilities - but for now it
> only knows how to mimic Verilog $readmemb/h.

It seems to be enough for simple stuff so I could use it.
It is licenced under Apache2.0, is it compatible with
other Free Software licences ? (and which ?)

yg
-- 
http://ygdes.com / http://yasep.org

On Tue, 19 Jan 2010 22:02:56 +0100, whygee
<y...@yg.yg> wrote:

>Jonathan Bromley wrote:
>>   http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip
>> One day, when there's less work to do, I intend to add a
>> few more file formats to its capabilities - but for now it
>> only knows how to mimic Verilog $readmemb/h.
>
>It seems to be enough for simple stuff so I could use it.

Nice of you to say so - it kept the Verilog community happy
for nearly two decades, so perhaps it ain't so bad :-)

>It is licenced under Apache2.0, is it compatible with
>other Free Software licences ? (and which ?)

The point of the Apache licence, as I understand it, is
to say "do what the blazes you like with this, but don't
blame me if it doesn't do what you want".  Unlike GPL 
it permits you to include the code in closed-source
commercial products if you so choose (I think) but
does not allow you to claim it as your own, or to
restrict its use by others.

Legal experts may dispute this.  If so, perhaps they
could be kind enough to tell me what I should do to 
get the effect I describe in the previous paragraph.
I really, really don't want to be sued because there's
a bug in a piece of code I posted via Usenet; but if
I give away some code, I really want to give it away -
no strings [*] attached.  Not even the manic-obsessive
doctrinaire-libertarian strings that are attached 
by GPL.

[*] Puppet-style strings, that is.  Arrays of ASCII
    characters are OK :-)
-- 
Jonathan Bromley