Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA | Post Route Simulation for IP CORES
There are 1 messages in this thread.
You are currently looking at messages 0 to 1.
Post Route Simulation for IP CORES - Rishvanth - 2010-01-19 14:08:00
Hi all, I created a project which contains some xilinx IP CORES. I have successfully tested the behavioral simulation but I'm unable to get the post route simulation. Is there a way to get a post route simulation for projects containing IP CORES? Thanks --------------------------------------- Sent through http://www.FPGARelated.com
