When a preformed post route simulation it gave me
this warnings. I amhaving trouble in understanding them and why these warning come up. 

WARNING:Timing:3224 - The clock clkf_4 associated with OFFSET = IN 800 nsBEFORE COMP "clkf_4"; does not clock any
   registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 800 ns BEFORE COMP"clkf_4"; ignored during timing analysis

Thank you for the help in advance	   
					
---------------------------------------		
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On Sat, 23 Jan 2010 17:26:13 -0600,
"akshayvreddy"
<akshayvreddy@n_o_s_p_a_m.gmail.com> wrote:

>When a preformed post route simulation it gave me this warnings. I am
>having trouble in understanding them and why these warning come up. 
>
>WARNING:Timing:3224 - The clock clkf_4 associated with OFFSET = IN 800 ns
>BEFORE COMP "clkf_4"; does not clock any
>   registered input components.
>WARNING:Timing:3225 - Timing constraint OFFSET = IN 800 ns BEFORE COMP
>"clkf_4"; ignored during timing analysis
>
>Thank you for the help in advance	   

These outputs are from fpga tools (map and/or par) not from post-route
simulation. Post route simulation means getting the doing a gate level
simulation by annotating the gate level verilog output of PAR with the
SDF generated at the same time.
The first warning is telling you that the clock constraint you
generated in the UCF file has a problem ie the name doesn't match any
clocks or it's not connected to any nets. You probably misspelled it.
The second one is telling you pretty much the same thing ie because
the said clock doesn't clock any flops, the timing constraint is being
ignored during PAR.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com