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Comp.Arch.FPGA | FPGA Editor - Post Route Simulation after changes in Ncd file

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

FPGA Editor - Post Route Simulation after changes in Ncd file - Charles - 2010-01-28 13:55:00

Hi All,
       I am new to the FPGA design flow. Now I am working on FPGA editor tomake changes in the design. Once I make changes in the ncd file i can haveeither a modified ncd file or a bit file from it (using Bitgen). 

My question is that is it possible to do post route simulation from any ofthese two files or is there any other way to do it??

Thanks in Advance,

Charles.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com



Re: FPGA Editor - Post Route Simulation after changes in Ncd file - kkoorndyk - 2010-01-29 11:03:00

On Jan 28, 1:55=A0pm, "Charles"
<charlesdlam...@gmail.com> wrote:
> Hi All,
> =A0 =A0 =A0 =A0I am new to the FPGA design flow. Now I am working on FPGA=
 editor to
> make changes in the design. Once I make changes in the ncd file i can hav=
e
> either a modified ncd file or a bit file from it (using Bitgen).
>
> My question is that is it possible to do post route simulation from any o=
f
> these two files or is there any other way to do it??
>
> Thanks in Advance,
>
> Charles.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Yep.  Look at the Command Line Tools User Guide (UG628) for the NetGen
function.
www.xilinx.com/support/documentation/sw.../xilinx11/devref.pdf
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Re: FPGA Editor - Post Route Simulation after changes in Ncd file - Jim Wu - 2010-02-27 12:15:00

On Jan 28, 1:55=A0pm, "Charles"
<charlesdlam...@gmail.com> wrote:
> Hi All,
> =A0 =A0 =A0 =A0I am new to the FPGA design flow. Now I am working on FPGA=
 editor to
> make changes in the design. Once I make changes in the ncd file i can hav=
e
> either a modified ncd file or a bit file from it (using Bitgen).
>
> My question is that is it possible to do post route simulation from any o=
f
> these two files or is there any other way to do it??
>
> Thanks in Advance,
>
> Charles.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

You can run "netgen" command with the modified NCD to generate a
Verilog or VHDL simulation model.

Cheers,
Jim
http://myfpgablog.blogspot.com/
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.