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Comp.Arch.FPGA | Single Port Rom created by Core Generator configurable by generic values!!!!

There are 9 messages in this thread.

You are currently looking at messages 0 to 9.

Single Port Rom created by Core Generator configurable by generic values!!!! - bellatoise - 2010-02-01 07:33:00

Hi,

My query is the next:
I'm working with Xilinx Ise Design Suite 11.1.
I need some ROMS with differents values of depth, width and initializationfiles that I want to instantiate in one proyect. I need a generic ROM, so Icreated one with Core Generator and I got its HDL code  using View HDLfunctional Model.
Then I introduced the values of width, depth and initialization file likegenerics values. In the proyect, I generated the ROMS intantiating this HDLcode, each one with differents values. 

When I sintetize the proyect appears some warnings like those:
WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not attachto Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
WARNING:Xst:616 - Invalid property "depth 3": Did not attach toGen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
WARNING:Xst:616 - Invalid property "width 8": Did not attach toGen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.

 

Is there another way to get a ROM with Core Generator so that it can beinstantiated in the proyect and form there I can generate differents ROMssince te core that I created with differents the values of width, depth and  initialization file??

 

 

Thank you 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com



Re: Single Port Rom created by Core Generator configurable by generic values!!!! - Enes Erdin - 2010-02-01 09:45:00

On 1 =C5=9Eubat, 14:33, "bellatoise"
<arianapo...@gmail.com> wrote:
> Hi,
>
> My query is the next:
> I'm working with Xilinx Ise Design Suite 11.1.
> I need some ROMS with differents values of depth, width and initializatio=
n
> files that I want to instantiate in one proyect. I need a generic ROM, so=
 I
> created one with Core Generator and I got its HDL code =C2=A0using View H=
DL
> functional Model.
> Then I introduced the values of width, depth and initialization file like
> generics values. In the proyect, I generated the ROMS intantiating this H=
DL
> code, each one with differents values.
>
> When I sintetize the proyect appears some warnings like those:
> WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not atta=
ch
> to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> WARNING:Xst:616 - Invalid property "depth 3": Did not attach to
> Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> WARNING:Xst:616 - Invalid property "width 8": Did not attach to
> Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>
> Is there another way to get a ROM with Core Generator so that it can be
> instantiated in the proyect and form there I can generate differents ROMs
> since te core that I created with differents the values of width, depth a=
nd
> =C2=A0 initialization file??
>
> Thank you
>
> --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0
> Posted throughhttp://www.FPGARelated.com

Take a look at creating ROMs using textio operations, that is, create
your own ROM via VHDL. I hope it will solve your problem.

--enes
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - Enes Erdin - 2010-02-01 09:55:00

On 1 =C5=9Eubat, 16:45, Enes Erdin
<eneser...@gmail.com> wrote:
> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com> wrote:
>
>
>
> > Hi,
>
> > My query is the next:
> > I'm working with Xilinx Ise Design Suite 11.1.
> > I need some ROMS with differents values of depth, width and initializat=
ion
> > files that I want to instantiate in one proyect. I need a generic ROM, =
so I
> > created one with Core Generator and I got its HDL code =C2=A0using View=
 HDL
> > functional Model.
> > Then I introduced the values of width, depth and initialization file li=
ke
> > generics values. In the proyect, I generated the ROMS intantiating this=
 HDL
> > code, each one with differents values.
>
> > When I sintetize the proyect appears some warnings like those:
> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not
at=
tach
> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to
> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> > WARNING:Xst:616 - Invalid property "width 8": Did not attach to
> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>
> > Is there another way to get a ROM with Core Generator so that it can be
> > instantiated in the proyect and form there I can generate differents RO=
Ms
> > since te core that I created with differents the values of width, depth=
 and
> > =C2=A0 initialization file??
>
> > Thank you
>
> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0
> > Posted throughhttp://www.FPGARelated.com
>
> Take a look at creating ROMs using textio operations, that is, create
> your own ROM via VHDL. I hope it will solve your problem.
>
> --enes

> via VHDL

make that HDL

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - bellatoise - 2010-02-01 11:02:00

>On 1 =C5=9Eubat, 16:45, Enes Erdin
<eneser...@gmail.com> wrote:
>> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com>
wrote:
>>
>>
>>
>> > Hi,
>>
>> > My query is the next:
>> > I'm working with Xilinx Ise Design Suite 11.1.
>> > I need some ROMS with differents values of depth, width andinitializat=
>ion
>> > files that I want to instantiate in one proyect. I need a generic ROM,=
>so I
>> > created one with Core Generator and I got its HDL code =C2=A0usingView=
> HDL
>> > functional Model.
>> > Then I introduced the values of width, depth and initialization fileli=
>ke
>> > generics values. In the proyect, I generated the ROMS intantiatingthis=
> HDL
>> > code, each one with differents values.
>>
>> > When I sintetize the proyect appears some warnings like those:
>> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did
notat=
>tach
>> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach to
>> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>> > WARNING:Xst:616 - Invalid property "width 8": Did not attach to
>> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>>
>> > Is there another way to get a ROM with Core Generator so that it canbe
>> > instantiated in the proyect and form there I can generate differentsRO=
>Ms
>> > since te core that I created with differents the values of width,depth=
> and
>> > =C2=A0 initialization file??
>>
>> > Thank you
>>
>> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0 =C2=A0
>> > Posted throughhttp://www.FPGARelated.com
>>
>> Take a look at creating ROMs using textio operations, that is, create
>> your own ROM via VHDL. I hope it will solve your problem.
>>
>> --enes
>
>> via VHDL
>
>make that HDL
>

Ok, I can do my own ROM  via HDL but I need to use a CORE. What can I do??
I have to use a Core for demands of the proyect.
Thank you 
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - Rob Gaddi - 2010-02-01 12:23:00

On Mon, 01 Feb 2010 10:02:09 -0600
"bellatoise" <arianaponte@n_o_s_p_a_m.gmail.com> wrote:

> >On 1 =C5=9Eubat, 16:45, Enes Erdin <eneser...@gmail.com> wrote:
> >> On 1 =C5=9Eubat, 14:33, "bellatoise" <arianapo...@gmail.com>
wrote:
> >>
> >>
> >>
> >> > Hi,
> >>
> >> > My query is the next:
> >> > I'm working with Xilinx Ise Design Suite 11.1.
> >> > I need some ROMS with differents values of depth, width and
> initializat=
> >ion
> >> > files that I want to instantiate in one proyect. I need a
> >> > generic ROM,
> =
> >so I
> >> > created one with Core Generator and I got its HDL code
> >> > =C2=A0using
> View=
> > HDL
> >> > functional Model.
> >> > Then I introduced the values of width, depth and initialization
> >> > file
> li=
> >ke
> >> > generics values. In the proyect, I generated the ROMS
> >> > intantiating
> this=
> > HDL
> >> > code, each one with differents values.
> >>
> >> > When I sintetize the proyect appears some warnings like those:
> >> > WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif":
Did
> >> > not
> at=
> >tach
> >> > to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> >> > WARNING:Xst:616 - Invalid property "depth 3": Did not attach
to
> >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> >> > WARNING:Xst:616 - Invalid property "width 8": Did not attach
to
> >> > Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> >>
> >> > Is there another way to get a ROM with Core Generator so that it
> >> > can
> be
> >> > instantiated in the proyect and form there I can generate
> >> > differents
> RO=
> >Ms
> >> > since te core that I created with differents the values of width,
> depth=
> > and
> >> > =C2=A0 initialization file??
> >>
> >> > Thank you
> >>
> >> > --------------------------------------- =C2=A0 =C2=A0 =C2=A0
> >> > =C2=A0 Posted throughhttp://www.FPGARelated.com
> >>
> >> Take a look at creating ROMs using textio operations, that is,
> >> create your own ROM via VHDL. I hope it will solve your problem.
> >>
> >> --enes
> >
> >> via VHDL
> >
> >make that HDL
> >
> 
> Ok, I can do my own ROM  via HDL but I need to use a CORE. What can I
> do?? I have to use a Core for demands of the proyect.
> Thank you 
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Ahhh, this is a _homework_ problem.  You should have said that earlier.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - RCIngham - 2010-02-01 12:26:00

>
>Ok, I can do my own ROM  via HDL but I need to use a CORE. What can Ido??
>I have to use a Core for demands of the proyect.
>Thank you 
>

It's very difficult to 'genericise' the CoreGen outputs, although certainlypossible for some types of cores.

You could have a 'generic wrapper' that calls up different CoreGen outputs,for instance in VHDL using conditional generate statements (assuming thatthe company coding standards let you).

Or you could just take the pain...
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - Rob Gaddi - 2010-02-01 12:34:00

On Mon, 01 Feb 2010 11:26:59 -0600
"RCIngham" <robert.ingham@n_o_s_p_a_m.gmail.com> wrote:

> 
> >
> >Ok, I can do my own ROM  via HDL but I need to use a CORE. What can I
> do??
> >I have to use a Core for demands of the proyect.
> >Thank you 
> >
> 
> It's very difficult to 'genericise' the CoreGen outputs, although
> certainly possible for some types of cores.
> 
> You could have a 'generic wrapper' that calls up different CoreGen
> outputs, for instance in VHDL using conditional generate statements
> (assuming that the company coding standards let you).
> 
> Or you could just take the pain...
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Actually had to do something like that on a project I'm working on right
now.  I was building up a variable rate decimator (2:1 steps) by just
chaining together 7 FIR halfbands (about the simplest block I'd be
willing to call in a CoreGen on), and muxing between their outputs.
All the filters had the same set of coefficients, but they all needed
to be Gen'd independently to accomodate different input rates.

Ultimately the best answer turned out to be writing a Python script
that writes out the 7 nearly identical .XCO files, then calling CoreGen
from the command line on all of them.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - Mike Treseler - 2010-02-01 17:14:00

bellatoise wrote:

> Ok, I can do my own ROM  via HDL but I need to use a CORE. What can I do??
> I have to use a Core for demands of the proyect.
> Thank you 

If I synthesize working HDL code for a specific device, I have a core.

core   = synthesis - source.

If I have the source code for some rom, say
http://mysite.verizon.net/miketreseler/sync_rom.vhd
Then I can make rom cores for brands A-X by running synthesis
and then hiding the source code.

       -- Mike Treseler
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Single Port Rom created by Core Generator configurable by generic values!!!! - CP - 2010-02-02 04:01:00

On 1 Feb., 13:33, "bellatoise"
<arianapo...@gmail.com> wrote:
> Hi,
>
> My query is the next:
> I'm working with Xilinx Ise Design Suite 11.1.
> I need some ROMS with differents values of depth, width and initializatio=
n
> files that I want to instantiate in one proyect. I need a generic ROM, so=
 I
> created one with Core Generator and I got its HDL code =A0using View HDL
> functional Model.
> Then I introduced the values of width, depth and initialization file like
> generics values. In the proyect, I generated the ROMS intantiating this H=
DL
> code, each one with differents values.
>
> When I sintetize the proyect appears some warnings like those:
> WARNING:Xst:616 - Invalid property "archivo_inic CUATR.mif": Did not atta=
ch
> to Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> WARNING:Xst:616 - Invalid property "depth 3": Did not attach to
> Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
> WARNING:Xst:616 - Invalid property "width 8": Did not attach to
> Gen_circuito_realimentacion[3].Multiplicador_intermedio.M_int.
>
> Is there another way to get a ROM with Core Generator so that it can be
> instantiated in the proyect and form there I can generate differents ROMs
> since te core that I created with differents the values of width, depth a=
nd
> =A0 initialization file??
>
> Thank you
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

don't know whether that helps you, but you can easily generate any ROM
using vMAGIC, look at the demo page on http:// vmagic.sf.net
______________________________
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