Could some Xilinx guru please help ? I have the
following module
synthesized on Xilinix ISE 11.1. I am getting a message at the end of
synthesis that no clock exists for design - could some please kindly
explain what it means ?

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    00:08:55 02/02/2010
// Design Name:
// Module Name:    GetTail
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GetTail(
    input [0:0] clock,
    input [0:511] inarr,
    input [0:31] inpriority,
    input [0:31] intail,
    input [0:31] innum,
    input [0:31] toppriority,
    input [0:31] outtail
    );

parameter MAX = 512;
parameter DATA_WIDTH = 32;

reg [0 : 31] localtail;

initial
 begin
  localtail = intail;
 end


always @ (posedge clock)
  if(inpriority == 0)
   begin
      if(innum > 0  &&
         inarr[localtail] == 0 &&
         inarr[localtail + 1] == 1)
        begin
           localtail = localtail + 1;
        end

      else if(innum > 0 &&
             localtail == MAX - 1 &&
             inarr[localtail] == 0)
         begin
           localtail = 0;
         end
  end
  else if(inpriority > 0)
   begin
    localtail = toppriority;
   end

endmodule

Any hints, suggestions would be of immense help - thanks in advance.

On Feb 2, 7:28=A0am, Daku
<dakup...@gmail.com> wrote:
> Could some Xilinx guru please help ? I have the following module
> synthesized on Xilinix ISE 11.1. I am getting a message at the end of
> synthesis that no clock exists for design - could some please kindly
> explain what it means ?
>
> `timescale 1ns / 1ps
> /////////////////////////////////////////////////////////////////////////=
// ///////
> // Company:
> // Engineer:
> //
> // Create Date: =A0 =A000:08:55 02/02/2010
> // Design Name:
> // Module Name: =A0 =A0GetTail
> // Project Name:
> // Target Devices:
> // Tool versions:
> // Description:
> //
> // Dependencies:
> //
> // Revision:
> // Revision 0.01 - File Created
> // Additional Comments:
> //
> /////////////////////////////////////////////////////////////////////////=
// ///////
> module GetTail(
> =A0 =A0 input [0:0] clock,
> =A0 =A0 input [0:511] inarr,
> =A0 =A0 input [0:31] inpriority,
> =A0 =A0 input [0:31] intail,
> =A0 =A0 input [0:31] innum,
> =A0 =A0 input [0:31] toppriority,
> =A0 =A0 input [0:31] outtail
> =A0 =A0 );
>
> parameter MAX =3D 512;
> parameter DATA_WIDTH =3D 32;
>
> reg [0 : 31] localtail;
>
> initial
> =A0begin
> =A0 localtail =3D intail;
> =A0end
>
> always @ (posedge clock)
> =A0 if(inpriority =3D=3D 0)
> =A0 =A0begin
> =A0 =A0 =A0 if(innum > 0 =A0&&
> =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0 &&
> =A0 =A0 =A0 =A0 =A0inarr[localtail + 1] =3D=3D 1)
> =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0localtail =3D localtail + 1;
> =A0 =A0 =A0 =A0 end
>
> =A0 =A0 =A0 else if(innum > 0 &&
> =A0 =A0 =A0 =A0 =A0 =A0 =A0localtail =3D=3D MAX - 1 &&
> =A0 =A0 =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0)
> =A0 =A0 =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0 =A0localtail =3D 0;
> =A0 =A0 =A0 =A0 =A0end
> =A0 end
> =A0 else if(inpriority > 0)
> =A0 =A0begin
> =A0 =A0 localtail =3D toppriority;
> =A0 =A0end
>
> endmodule
>
> Any hints, suggestions would be of immense help - thanks in advance.

any designs with NO OUTPUT ports will be considered EMTPY designs
so EVERYTHING is optimized away what leads to error message.

Antti

Dear Sir/Madam,
I have already tried with the output port, but the result is exactly
the same.
Thank you.
On Feb 2, 10:43 am, Antti <antti.luk...@googlemail.com> wrote:

> any designs with NO OUTPUT ports will be considered EMTPY designs
> so EVERYTHING is optimized away what leads to error message.
>
> Antti

On Mon, 1 Feb 2010 21:28:38 -0800 (PST), Daku
<d...@gmail.com>
wrote:

...

Before you try to synthesize anything, you should first simulat what
you wrote (or what a tool generated for you?) Your module has no
outputs (but a port named outtail, typo?) so all  logic (including
your clock signal) will be removed. If you put this module in a
testbench and try to get to what ever it's calculating you will figure
this out very quickly.

Also the coding style of the module is quite error-prone. Invest some
time in learning how to write synthesizable rtl for the time you'll
actually do synthesis so  that you won't have to revise all your code
after you think you're done typing.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Dear Sir/Madam,
The code that I posted is actually a task in a large
Verilog module. This large module was simulated
separately with ModelSim 6.5c and open-source
Icarus Verilog 0.9.1. In both cases, the simulation
results were as I had expected them to be.

It was only after these two simulations were run, code
modified and re-run a number of times that I tried this
synthesis with Xilinx ISE 11.1. Unfortunately, when I
tried the whole design, Xilinx gave a 'out of memory'
error at the end, forcing me to divide the module into sub-modules.

Indeed, the 'outtail' is a typo, but I had already corrected
and tried synthesis before the original post. I fully agree
with what you say, but for some reason that I do not
understand, Xilinx's XST thinks this is an empty module.

Thank you.

On Feb 3, 11:09 am, Muzaffer Kal <k...@dspia.com> wrote:
> On Mon, 1 Feb 2010 21:28:38 -0800 (PST), Daku <dakup...@gmail.com>
> wrote:
>
> ...
>
> Before you try to synthesize anything, you should first simulat what
> you wrote (or what a tool generated for you?) Your module has no
> outputs (but a port named outtail, typo?) so all  logic (including
> your clock signal) will be removed. If you put this module in a
> testbench and try to get to what ever it's calculating you will figure
> this out very quickly.
>
> Also the coding style of the module is quite error-prone. Invest some
> time in learning how to write synthesizable rtl for the time you'll
> actually do synthesis so  that you won't have to revise all your code
> after you think you're done typing.
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

On Feb 3, 11:02=A0am, Daku
<dakup...@gmail.com> wrote:
> Dear Sir/Madam,
> The code that I posted is actually a task in a large
> Verilog module. This large module was simulated
> separately with ModelSim 6.5c and open-source
> Icarus Verilog 0.9.1. In both cases, the simulation
> results were as I had expected them to be.
>
> It was only after these two simulations were run, code
> modified and re-run a number of times that I tried this
> synthesis with Xilinx ISE 11.1. Unfortunately, when I
> tried the whole design, Xilinx gave a 'out of memory'
> error at the end, forcing me to divide the module into sub-modules.
>
> Indeed, the 'outtail' is a typo, but I had already corrected
> and tried synthesis before the original post. I fully agree
> with what you say, but for some reason that I do not
> understand, Xilinx's XST thinks this is an empty module.
>
> Thank you.
>
> On Feb 3, 11:09 am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > On Mon, 1 Feb 2010 21:28:38 -0800 (PST), Daku <dakup...@gmail.com>
> > wrote:
>
> > ...
>
> > Before you try to synthesize anything, you should first simulat what
> > you wrote (or what a tool generated for you?) Your module has no
> > outputs (but a port named outtail, typo?) so all =A0logic (including
> > your clock signal) will be removed. If you put this module in a
> > testbench and try to get to what ever it's calculating you will figure
> > this out very quickly.
>
> > Also the coding style of the module is quite error-prone. Invest some
> > time in learning how to write synthesizable rtl for the time you'll
> > actually do synthesis so =A0that you won't have to revise all your code
> > after you think you're done typing.
> > --
> > Muzaffer Kal
>
> > DSPIA INC.
> > ASIC/FPGA Design Services
>
> >http://www.dspia.com
>
>

Maybe if you post the corrected code as rejected by Xilinx
someone can comment on it.  I don't see any assignment made
to the "output" outtail in the code you originally posted.

regards,
Gabor

On Feb 1, 9:28=A0pm, Daku
<dakup...@gmail.com> wrote:
> Could some Xilinx guru please help ? I have the following module
> synthesized on Xilinix ISE 11.1. I am getting a message at the end of
> synthesis that no clock exists for design - could some please kindly
> explain what it means ?
>
> `timescale 1ns / 1ps
> /////////////////////////////////////////////////////////////////////////=
//=AD///////
> // Company:
> // Engineer:
> //
> // Create Date: =A0 =A000:08:55 02/02/2010
> // Design Name:
> // Module Name: =A0 =A0GetTail
> // Project Name:
> // Target Devices:
> // Tool versions:
> // Description:
> //
> // Dependencies:
> //
> // Revision:
> // Revision 0.01 - File Created
> // Additional Comments:
> //
> /////////////////////////////////////////////////////////////////////////=
//=AD///////
> module GetTail(
> =A0 =A0 input [0:0] clock,
> =A0 =A0 input [0:511] inarr,
> =A0 =A0 input [0:31] inpriority,
> =A0 =A0 input [0:31] intail,
> =A0 =A0 input [0:31] innum,
> =A0 =A0 input [0:31] toppriority,
> =A0 =A0 input [0:31] outtail
> =A0 =A0 );
>
> parameter MAX =3D 512;
> parameter DATA_WIDTH =3D 32;
>
> reg [0 : 31] localtail;
>
> initial
> =A0begin
> =A0 localtail =3D intail;
> =A0end
>
> always @ (posedge clock)
> =A0 if(inpriority =3D=3D 0)
> =A0 =A0begin
> =A0 =A0 =A0 if(innum > 0 =A0&&
> =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0 &&
> =A0 =A0 =A0 =A0 =A0inarr[localtail + 1] =3D=3D 1)
> =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0localtail =3D localtail + 1;
> =A0 =A0 =A0 =A0 end
>
> =A0 =A0 =A0 else if(innum > 0 &&
> =A0 =A0 =A0 =A0 =A0 =A0 =A0localtail =3D=3D MAX - 1 &&
> =A0 =A0 =A0 =A0 =A0 =A0 =A0inarr[localtail] =3D=3D 0)
> =A0 =A0 =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0 =A0localtail =3D 0;
> =A0 =A0 =A0 =A0 =A0end
> =A0 end
> =A0 else if(inpriority > 0)
> =A0 =A0begin
> =A0 =A0 localtail =3D toppriority;
> =A0 =A0end
>
> endmodule
>
> Any hints, suggestions would be of immense help - thanks in advance.

In your code you wrote:

>  input [0:0] clock,
>  ....
> always @ (posedge clock)

These are not the same thing.  The first usage is a vector with single
bit number of 0 which is expanded as "clock[0]".

Ed McGettigan
--
Xilinx Inc.

Dear All,
The solution is really simple. Instead of editing the source file as:
 module GetTail(
    input [0:0] clock,
    input [0:511] inarr,
    input [0:31] inpriority,
    input [0:31] intail,
    input [0:31] innum,
    input [0:31] toppriority,
    input [0:31] outtail
    );
 TO :
 module GetTail(
    input [0:0] clock,
    input [0:511] inarr,
    input [0:31] inpriority,
    input [0:31] intail,
    input [0:31] innum,
    input [0:31] toppriority,
    output [0:31] outtail
    );

Simply create a brand new project with the source code module declared
as:
 module GetTail(
    input [0:0] clock,
    input [0:511] inarr,
    input [0:31] inpriority,
    input [0:31] intail,
    input [0:31] innum,
    input [0:31] toppriority,
    output [0:31] outtail
    );
Synthesis works just fine after that.
Also, in response to one of the poster's queries, declare a
register as:
reg [0 : 31] outtailA;

and before the 'always' have:
assign outtail = outtailA;
Where the register outtailA gets assigned to appropriate
output values inside the 'always @ (posedge clock)' .
Thank you for your insightful comments.

On Feb 4, 1:43 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> In your code you wrote:
>
> >  input [0:0] clock,
> >  ....
> > always @ (posedge clock)
>
> These are not the same thing.  The first usage is a vector with single
> bit number of 0 which is expanded as "clock[0]".
>
> Ed McGettigan
> --
> Xilinx Inc.