Hi,
I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data streamis coming in one byte at a time, but I do have about 8-10 clock cyclesbetween each byte (still tbd!). 

If I want to save area, is it better to use a CRC that works byte per byteor bit per bit? 

Also, any idea where I could find code for the standard polynomials?

Thanks!
Diego	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Wed, 03 Feb 2010 07:21:13 -0600, dlopez
wrote:

> Hi,
> I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data
> stream is coming in one byte at a time, but I do have about 8-10 clock
> cycles between each byte (still tbd!).
> 
> If I want to save area, is it better to use a CRC that works byte per
> byte or bit per bit?
> 
> Also, any idea where I could find code for the standard polynomials?
> 
> Thanks!
> Diego
> 					
> --------------------------------------- Posted through
> http://www.FPGARelated.com

There is a great polynomial generator on the web,

http://www.easics.com/webtools/crctool

"dlopez"
<d@n_o_s_p_a_m.designgame.ca> writes:

> If I want to save area, is it better to use a CRC that works byte
> per byte or bit per bit?

Per bit as it is simply a shift register with xor gates at the
polynomial positions.


Here is a sample program to symbolically convert a serial form to a
parallel form:

http://tinyurl.com/ygvenaz

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On Feb 3, 10:13=A0am, Petter Gustad
<newsmailco...@gustad.com> wrote:
> "dlopez" <d@n_o_s_p_a_m.designgame.ca> writes:
> > If I want to save area, is it better to use a CRC that works byte
> > per byte or bit per bit?
>
> Per bit as it is simply a shift register with xor gates at the
> polynomial positions.
>
> Here is a sample program to symbolically convert a serial form to a
> parallel form:
>
> http://tinyurl.com/ygvenaz

To do a serial CRC calculation requires a state machine to control
it.  A parallel CRC has to perform multiple xors for each bit using
extra logic compared to the bit serial version, the difference
depending on the size of the CRC.  The question is which uses more
logic, a byte parallel CRC generator or the control logic for the
state machine.  Depending on the CRC chosen, I bet it is close to a
wash, but the only way to know for sure is to build both and see.

In article
<1...@t21g2000vbo.googlegroups.com>,
 rickman <g...@gmail.com> writes:

>To do a serial CRC calculation requires a state machine to control
>it.  A parallel CRC has to perform multiple xors for each bit using
>extra logic compared to the bit serial version, the difference
>depending on the size of the CRC.  The question is which uses more
>logic, a byte parallel CRC generator or the control logic for the
>state machine.  Depending on the CRC chosen, I bet it is close to a
>wash, but the only way to know for sure is to build both and see.

The bit serial CRC has a simple structure.  It can easily run
at a high clock rate.

The parallel CRC turns into an ugly cloud of XORs.  The details
depend upon the polynomial and how many bits you are processing
in parallel.  Expect it to turn into a good test case for the
placer and router.

If the OP doesn't have enough clocks to process things in
bit serial, it might work out better to do 2 bits in parallel
on each of 4 clocks.  I think that needs 4 inputs worst case
so it fits in one layer of LUT.  (I'm rusty on this, but years
ago I spent a lot of time in this area.  I think I've made all
possible screwups while writing software to check things.
There are a lot of wrong possibilities when you consider big
endian vs little endian, shifting right or left or ...)

-- 
These are my opinions, not necessarily my employer's.  I hate spam.

There is an article in Jan '10 issue of
CircuitCellar magazine ( page
40, http://www.scribd.com/doc/24890014/Circuit-Cellar-January-2010-TV
) that discusses different parallel CRC implementation methods.


Thanks,
Evgeni

>Hi,
>I need to implement CRC detection in a Spartan3 Xilinx FPGA. My datastream
>is coming in one byte at a time, but I do have about 8-10 clock cycles
>between each byte (still tbd!). 
>
>If I want to save area, is it better to use a CRC that works byte perbyte
>or bit per bit? 
>
>Also, any idea where I could find code for the standard polynomials?
>
>Thanks!
>Diego	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>
If you have 8-10 clock cycles, a serial implementation will most likely bethe the easiest and the least resource intensive. The architecture isessentially a shift register with XOR gates inserted between some of theflops. Like others have mentioned, web based CRC calculation tools can bevery useful when debugging the design.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com