Abby Brown wrote:
> "Eric Chomko" <p...@comcast.net> wrote in message 
> news:b...@o8g2000vbm.googlegroups.com...
>> Has anyone created a copy machine of an old system using an 
>> FPGA? I
>> was wondering if it would be possible to take an entire SWTPC 
>> 6800 and
>> compile the schematics and have it run on an FPGA board.? 
>> Wouldn't
>> even have to be the latest Xylinx product, I suspect.
> 
> Absolutely.  There a number of them.  This guy has done a PDP-4 
> and PDP-8,
> 
>     http://homepage.mac.com/dgcx/pdp4x/
> 
>     http://homepage.mac.com/dgcx/pdp4x/
> 
> I am in the process of doing a PDP-1.  My  background is high 
> performance computers so it is a high performance design. 
> Todays FPGAs and CAD allow a much more agressive implementation 
> than the original designers could afford and with far less 
> effort.  The original PDP-1s sold for about $100K in early 
> 1960s' dollars.  Mine will cost only a few hundred dollars to 
> build.
> 
> Those interested in the subject might also be interested in the 
> simh group,
> 
>     http://simh.trailing-edge.com/
> 
> which does simulators for legacy computers.

Re your background is high performance, what do you like best
about the PDP-1?  (Or haven't you got that far?)

/BAH

"jmfbahciv" <jmfbahciv@aol> wrote in message 
news:h...@news4.newsguy.com...
> Abby Brown wrote:
>> "Eric Chomko" <p...@comcast.net> wrote in message 
>> news:b...@o8g2000vbm.googlegroups.com...
>>> Has anyone created a copy machine of an old system using an 
>>> FPGA? I
>>> was wondering if it would be possible to take an entire 
>>> SWTPC 6800 and
>>> compile the schematics and have it run on an FPGA board.? 
>>> Wouldn't
>>> even have to be the latest Xylinx product, I suspect.
>>
>> Absolutely.  There a number of them.  This guy has done a 
>> PDP-4 and PDP-8,
>>
>>     http://homepage.mac.com/dgcx/pdp4x/
>>
>>     http://homepage.mac.com/dgcx/pdp4x/
>>
>> I am in the process of doing a PDP-1.  My  background is high 
>> performance computers so it is a high performance design. 
>> Todays FPGAs and CAD allow a much more agressive 
>> implementation than the original designers could afford and 
>> with far less effort.  The original PDP-1s sold for about 
>> $100K in early 1960s' dollars.  Mine will cost only a few 
>> hundred dollars to build.
>>
>> Those interested in the subject might also be interested in 
>> the simh group,
>>
>>     http://simh.trailing-edge.com/
>>
>> which does simulators for legacy computers.
>
> Re your background is high performance, what do you like best
> about the PDP-1?  (Or haven't you got that far?)
>
> /BAH

The best (and worst) is the PDP-1's simplicity.  It is easy to 
implement.  For the most part conditionals are decoupled from 
arithmetic operations.  That helps branches, which are always a 
bottleneck.

The single arithmetic register is a bottleneck.  Out of order 
execution, for example, is difficult when almost every 
instruction accesses the same register.  Other the other hand, 
if you treat memory as registers, which is feasible (there are 
only 4K words), you can do interesting things with out-of-order. 
RISC computers, such as ALPHA and MIPS, have compilers that help 
the hardware by ordering instructions.  With legacy software, 
you cannot do that.

For comparison, when I was a DECie, I did the instruction fetch 
and processing unit for a data flow VAX (never produced, 
unfortunately).  The number and complexity of instructions and 
the weirdness of a few made high performace difficult.  That was 
one of the reasons DEC developed ALPHA.

Gary

On Feb 5, 1:19=A0pm, Eric Chomko
<pne.cho...@comcast.net> wrote:
> Has anyone created a copy machine of an old system using an FPGA? I
> was wondering if it would be possible to take an entire SWTPC 6800 and
> compile the schematics and have it run on an FPGA board.? Wouldn't
> even have to be the latest Xylinx product, I suspect.

In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an
FPGA: Reconstructing an '80s-Era Home Computer with Programmable
Logic". The author describes his experience of designing a Apple II+
compatiable project.

Another project I know of is mentioned at:

http://vector-graphic.info/vg_links.aspx

This whole website is dedicated to Vector Graphic S-100 computers. The
link half way down the page is wrong but the project can be found at:

http://opencores.org/project,vg_z80_sbc

At this web is 8086 core:

http://www.ht-lab.com/freecores/cpu8086/cpu86.html

I believe the sample project with the core would be equivalent of a
8086 SBC running DOS.

Derek

On Feb 21, 2:02=A0pm, Derek Simmons
<dereks...@gmail.com> wrote:
> On Feb 5, 1:19=A0pm, Eric Chomko <pne.cho...@comcast.net> wrote:
>
> > Has anyone created a copy machine of an old system using an FPGA? I
> > was wondering if it would be possible to take an entire SWTPC 6800 and
> > compile the schematics and have it run on an FPGA board.? Wouldn't
> > even have to be the latest Xylinx product, I suspect.
>
> In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an
> FPGA: Reconstructing an '80s-Era Home Computer with Programmable
> Logic". The author describes his experience of designing a Apple II+
> compatiable project.
>
> Another project I know of is mentioned at:
>
> http://vector-graphic.info/vg_links.aspx
>
> This whole website is dedicated to Vector Graphic S-100 computers. The
> link half way down the page is wrong but the project can be found at:
>
> http://opencores.org/project,vg_z80_sbc
>
> At this web is 8086 core:
>
> http://www.ht-lab.com/freecores/cpu8086/cpu86.html
>
> I believe the sample project with the core would be equivalent of a
> 8086 SBC running DOS.
>
> Derek

NOT a FPGA but certainly a design I would like to see executed in FPGA
and very vintage
http://laughtonelectronics.com/arcana/BrideOfSonPg1.html

He used a 65C02 and a KIM as his starting point. The 65C02 was chosen
because all
of its unimplemented instructions became NOPs. If I have it right, he
then intercepts
the unused op codes and uses them for his own purposes like extending
the memory
addressing. It is an interesting design in that when you move the
microcode off the
main processor you can optimize the system for very specific tasks. In
his case he
used it for running Forth.

I guess the argument could be just do the entire thing in VDHL or use
the right processor
for the job.<grin> Instruction set problems seem to come up fairly
often. I *think* some
C implementations could use a separate hardware stack for instance.

Rick

On Feb 21, 8:02=A0pm, Rick
<richardcort...@gmail.com> wrote:
> On Feb 21, 2:02=A0pm, Derek Simmons <dereks...@gmail.com> wrote:
>
>
>
> > On Feb 5, 1:19=A0pm, Eric Chomko <pne.cho...@comcast.net> wrote:
>
> > > Has anyone created a copy machine of an old system using an FPGA? I
> > > was wondering if it would be possible to take an entire SWTPC 6800 an=
d
> > > compile the schematics and have it run on an FPGA board.? Wouldn't
> > > even have to be the latest Xylinx product, I suspect.
>
> > In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an
> > FPGA: Reconstructing an '80s-Era Home Computer with Programmable
> > Logic". The author describes his experience of designing a Apple II+
> > compatiable project.
>
> > Another project I know of is mentioned at:
>
> >http://vector-graphic.info/vg_links.aspx
>
> > This whole website is dedicated to Vector Graphic S-100 computers. The
> > link half way down the page is wrong but the project can be found at:
>
> >http://opencores.org/project,vg_z80_sbc
>
> > At this web is 8086 core:
>
> >http://www.ht-lab.com/freecores/cpu8086/cpu86.html
>
> > I believe the sample project with the core would be equivalent of a
> > 8086 SBC running DOS.
>
> > Derek
>
> NOT a FPGA but certainly a design I would like to see executed in FPGA
> and very vintagehttp://laughtonelectronics.com/arcana/BrideOfSonPg1.html
>
> He used a 65C02 and a KIM as his starting point. The 65C02 was chosen
> because all
> of its unimplemented instructions became NOPs. If I have it right, he
> then intercepts
> the unused op codes and uses them for his own purposes like extending
> the memory
> addressing. It is an interesting design in that when you move the
> microcode off the
> main processor you can optimize the system for very specific tasks. In
> his case he
> used it for running Forth.
>
> I guess the argument could be just do the entire thing in VDHL or use
> the right processor
> for the job.<grin> Instruction set problems seem to come up fairly
> often. I *think* some
> C implementations could use a separate hardware stack for instance.
>
> Rick

A hardware stack for C is a bit of a problem.  C tends to need a
rather large stack because of the stack frames used.  A language like
Forth, on the other hand, can get by with a very small hardware stack
because the stack usage tends to be minimal and subroutine nesting
does not automatically add to the data stack depth.  Instead, often
parameters that are passed into one routine are also passed onto the
next without duplication until they are consumed by the calculations
that need them.  In c every call copies every piece of data needed for
the lower level code creating stack "bloat" if you will.

There are any number of Forth CPU designs, many of which use a
hardware dedicated stack for data and another for addresses.

Rick

In comp.arch.fpga rickman
<g...@gmail.com> wrote:
(big snip)
 
> A hardware stack for C is a bit of a problem.  C tends to need a
> rather large stack because of the stack frames used.  

It depends, somewhat, on the programmer.  In K&R C, you couldn't
pass a struct, but instead a pointer to a struct.  That kept
the stack a little smaller, at least.  With C89, as with K&R, 
arrays (including automatic, allocated on the stack) had a 
constant dimension.  If I remember right, C99 added the ability
to dimension local automatic (stack) arrays with variables.
(Previously, a pointer on the stack and malloc() would have
been used, along with the requirement to remember free().)

> A language like
> Forth, on the other hand, can get by with a very small hardware stack
> because the stack usage tends to be minimal and subroutine nesting
> does not automatically add to the data stack depth.  Instead, often
> parameters that are passed into one routine are also passed onto the
> next without duplication until they are consumed by the calculations
> that need them.  In c every call copies every piece of data needed for
> the lower level code creating stack "bloat" if you will.

If you only pass pointers, it isn't so bad...

-- glen

On Feb 22, 2:27=A0pm, rickman
<gnu...@gmail.com> wrote:
> On Feb 21, 8:02=A0pm, Rick <richardcort...@gmail.com> wrote:
>
>
>
> > On Feb 21, 2:02=A0pm, Derek Simmons <dereks...@gmail.com> wrote:
>
> > > On Feb 5, 1:19=A0pm, Eric Chomko <pne.cho...@comcast.net> wrote:
>
> > > > Has anyone created a copy machine of an old system using an FPGA? I
> > > > was wondering if it would be possible to take an entire SWTPC 6800 =
and
> > > > compile the schematics and have it run on an FPGA board.? Wouldn't
> > > > even have to be the latest Xylinx product, I suspect.
>
> > > In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an
> > > FPGA: Reconstructing an '80s-Era Home Computer with Programmable
> > > Logic". The author describes his experience of designing a Apple II+
> > > compatiable project.
>
> > > Another project I know of is mentioned at:
>
> > >http://vector-graphic.info/vg_links.aspx
>
> > > This whole website is dedicated to Vector Graphic S-100 computers. Th=
e
> > > link half way down the page is wrong but the project can be found at:
>
> > >http://opencores.org/project,vg_z80_sbc
>
> > > At this web is 8086 core:
>
> > >http://www.ht-lab.com/freecores/cpu8086/cpu86.html
>
> > > I believe the sample project with the core would be equivalent of a
> > > 8086 SBC running DOS.
>
> > > Derek
>
> > NOT a FPGA but certainly a design I would like to see executed in FPGA
> > and very vintagehttp://laughtonelectronics.com/arcana/BrideOfSonPg1.htm=
l
>
> > He used a 65C02 and a KIM as his starting point. The 65C02 was chosen
> > because all
> > of its unimplemented instructions became NOPs. If I have it right, he
> > then intercepts
> > the unused op codes and uses them for his own purposes like extending
> > the memory
> > addressing. It is an interesting design in that when you move the
> > microcode off the
> > main processor you can optimize the system for very specific tasks. In
> > his case he
> > used it for running Forth.
>
> > I guess the argument could be just do the entire thing in VDHL or use
> > the right processor
> > for the job.<grin> Instruction set problems seem to come up fairly
> > often. I *think* some
> > C implementations could use a separate hardware stack for instance.
>
> > Rick
>
> A hardware stack for C is a bit of a problem. =A0C tends to need a
> rather large stack because of the stack frames used. =A0A language like
> Forth, on the other hand, can get by with a very small hardware stack
> because the stack usage tends to be minimal and subroutine nesting
> does not automatically add to the data stack depth. =A0Instead, often
> parameters that are passed into one routine are also passed onto the
> next without duplication until they are consumed by the calculations
> that need them. =A0In c every call copies every piece of data needed for
> the lower level code creating stack "bloat" if you will.

I'm pretty sure ALGOL and PL/I are far worse WRT to stack bloat than
is C.
But yes, nothing would beat FORTH unless you used assembly and only
architectures with HW stacks. Two being better than one (i.e. 6809 vs
6800).

> There are any number of Forth CPU designs, many of which use a
> hardware dedicated stack for data and another for addresses.

Years ago I worked as a research assistant with a professor doing High-
Level
Architectures. I suggested Forth and he sort of poo-pooed the idea
mostly
because his grant was from the Air Force and they were all about using
JOVIAL
at that time. This was pre-RISC days and the whole computer
architecture idea
based upon a high-level language never really took off. Nor did the
use of a medium
level language like Forth as far as I can tell.

Eric

In comp.arch.fpga Eric Chomko
<p...@comcast.net> wrote:
(snip)
 
> I'm pretty sure ALGOL and PL/I are far worse WRT to stack 
> bloat than is C.

ALGOL, PL/I, and C pretty much require local variables to 
be automatic.  (PL/I procedures without the RECURSIVE attribute
might get away with static allocation.)

Fortran up through Fortran 77 allowed local variables to be
statically allocated.  Without the RECURSIVE attribute, it
probably still does.

Other than passing of arguments, it depends on how you allocate
your variables.  PL/I has the STATIC attribute which will keep
variables off the stack, as does C.  Be careful with recursion, though.
For ALGOL, maybe you need internal procedures using variables from
outside, and to minimize actual local variables.  PL/I can easily
generate temporary variables, including arrays.

> But yes, nothing would beat FORTH unless you used assembly and only
> architectures with HW stacks. Two being better than one (i.e. 6809 vs
> 6800).

-- glen 

glen herrmannsfeldt wrote:
> In comp.arch.fpga rickman <g...@gmail.com> wrote:
> (big snip)
>  
>> A hardware stack for C is a bit of a problem.  C tends to need a
>> rather large stack because of the stack frames used.  
> 
> It depends, somewhat, on the programmer.  In K&R C, you couldn't
> pass a struct, but instead a pointer to a struct.  That kept
> the stack a little smaller, at least.  With C89, as with K&R, 
> arrays (including automatic, allocated on the stack) had a 
> constant dimension.  If I remember right, C99 added the ability
> to dimension local automatic (stack) arrays with variables.
> (Previously, a pointer on the stack and malloc() would have
> been used, along with the requirement to remember free().)
> 

And even though structs *can* be passed to and returned from 
functions, a programmer is *not* forced to do that. One can still 
pass the pointers to structs. One can still use "malloc()" and 
"free()" to allocate variable-size arrays. If you are an "old 
time" C programmer, this probably fits better in your way of 
thinking. In any case, if it is important to conserve stack space, 
the "good ole ways" can still be used.


-- 
+----------------------------------------+
|     Charles and Francis Richmond       |
|                                        |
|  plano dot net at aquaporin4 dot com   |
+----------------------------------------+

Eric Chomko wrote:
> 
> I'm pretty sure ALGOL and PL/I are far worse WRT to stack bloat than
> is C.

PL/I can be, but doesn't have to be.  If the arguments of a procedure 
match the parameters, only the argument address (and possibly a 
descriptor address for strings structures, and arrays) is passed.  If 
the argument doesn't match, the compiler nicely copies it to a "dummy 
argument" that does.  As usual, the programmer needs to have some idea 
what's going on.