Hi all,

as the title says I have to read some information stored in UDP packet
with an FPGA. Now I'm evaluating 3 options:

1) Use an external processor and send data to FPGA through dedicated
lines
2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
since I'm working on a Xilinx)
3) Write an hardware implementation of the IP stack, or at least of he
part of the stack I need to read those packets

What are the pros and cons of each solution? Can you suggest me others
way to do that?

Thanks all

Dek

Dek <d...@gmail.com> wrote:
 
> as the title says I have to read some information stored in UDP packet
> with an FPGA. Now I'm evaluating 3 options:
 
> 1) Use an external processor and send data to FPGA through dedicated
> lines
> 2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
> since I'm working on a Xilinx)
> 3) Write an hardware implementation of the IP stack, or at least of he
> part of the stack I need to read those packets

UDP is much easier than TCP, so a good choice.  Other than accepting
the actual data, the complications are doing ARP.  That can easily
be done in another processor.  Any machine on the same subnet
can do it with the appropriate permanent entry in the ARP table.
If your system already has a processor on the same ethernet
but with a different network connection, this would be the easiest.

picoblaze is probably enough to send/receive ARP and otherwise
coordinate reception of the UDP data.  

It could even be done with a more ordinary state machine.  
(That would count as option 3.) 

> What are the pros and cons of each solution? Can you suggest 
> me others way to do that?

-- glen

On Feb 10, 8:04=A0am, Dek
<daniele.deq...@gmail.com> wrote:
> Hi all,
>
> as the title says I have to read some information stored in UDP packet
> with an FPGA. Now I'm evaluating 3 options:
>
> 1) Use an external processor and send data to FPGA through dedicated
> lines
> 2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
> since I'm working on a Xilinx)
> 3) Write an hardware implementation of the IP stack, or at least of he
> part of the stack I need to read those packets
>
> What are the pros and cons of each solution? Can you suggest me others
> way to do that?
>
> Thanks all
>
> Dek



UDP is very simple.  I have some designs that use a PicoBlaze to deal
with multiple streams of UDP packets that are multicast on a Gigabit
Ethernet VLAN.  Those designs are just processing the headers and
diverting the packets of interest to the FPGA fabric for more
processing.  Everything else is sent up the Linux network stack for
the PowerPC to deal with.  If you only care about the UDP data, you
don't need to do that.

I also have designs that use the FPGA fabric to directly deal with the
data from the EMAC with out using a processor at all.  Those are only
dealing with UDP and ICMP, and were simple and straight forward.

I would go for either option 2 or 3.  I don't know enough about your
other constraints to pick between those two.

What FPGA are you using?

Regards,

John McCaskill
www.FasterTechnology.com

John McCaskill <j...@gmail.com>
wrote:
(snip)
 
> I also have designs that use the FPGA fabric to directly deal with the
> data from the EMAC with out using a processor at all.  Those are only
> dealing with UDP and ICMP, and were simple and straight forward.

What do you do about ARP?

You won't get the packets unless ARP tells where to send them.

-- glen

Dek <d...@gmail.com> writes:

>Hi all,

>as the title says I have to read some information stored in UDP packet
>with an FPGA. Now I'm evaluating 3 options:

>1) Use an external processor and send data to FPGA through dedicated
>lines
>2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
>since I'm working on a Xilinx)
>3) Write an hardware implementation of the IP stack, or at least of he
>part of the stack I need to read those packets

>What are the pros and cons of each solution? Can you suggest me others
>way to do that?

>Thanks all

>Dek

	How fast is the UDP stream (gig or will 10/100 and low throughput do)?
Does your board already have an ethernet PHY or do you need to add one just
for this? If the volume and speed are both low (i.e. 100 or less) there was
a spi interfaced PIC 10/100 board referenced here a while back. That may be 
your cheapest solution (the one referenced here is about $20 and Wiznet makes
a bunch more that are a little more expensive). I don't think it will do 
anywhere near wire speed, but if your traffic is small enough that may be 
the easiest solution (someone else does the IP heavy lifting such as it is and
worries about things like arp :-)). 

Peter Van Epp

On 11 Feb, 01:12, van...@sfu.ca (Peter Van Epp)
wrote:
> Dek <daniele.deq...@gmail.com> writes:
> >Hi all,
> >as the title says I have to read some information stored in UDP packet
> >with an FPGA. Now I'm evaluating 3 options:
> >1) Use an external processor and send data to FPGA through dedicated
> >lines
> >2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
> >since I'm working on a Xilinx)
> >3) Write an hardware implementation of the IP stack, or at least of he
> >part of the stack I need to read those packets
> >What are the pros and cons of each solution? Can you suggest me others
> >way to do that?
> >Thanks all
> >Dek
>
> =A0 =A0 =A0 =A0 How fast is the UDP stream (gig or will 10/100 and low th=
roughput do)?
> Does your board already have an ethernet PHY or do you need to add one ju=
st
> for this? If the volume and speed are both low (i.e. 100 or less) there w=
as
> a spi interfaced PIC 10/100 board referenced here a while back. That may =
be
> your cheapest solution (the one referenced here is about $20 and Wiznet m=
akes
> a bunch more that are a little more expensive). I don't think it will do
> anywhere near wire speed, but if your traffic is small enough that may be
> the easiest solution (someone else does the IP heavy lifting such as it i=
s and
> worries about things like arp :-)).
>
> Peter Van Epp

Thanks you all for the replies,

I'm working on an embedded sistem (NI PXIe) and the FPGA is a Virtex5
mounted on a Flex Rio board. I decided to add an SNTP client on the
controller PC (wich runs NI real time software) and then comunicate
the time information through the backplane. I think it's the easiest
solution.

Bye

Dek

On 10 Feb, 16:31, glen herrmannsfeldt
<g...@ugcs.caltech.edu> wrote:
> John McCaskill <jhmccask...@gmail.com> wrote:
>
> (snip)
>
> > I also have designs that use the FPGA fabric to directly deal with the
> > data from the EMAC with out using a processor at all. =A0Those are only
> > dealing with UDP and ICMP, and were simple and straight forward.
>
> What do you do about ARP?
>
> You won't get the packets unless ARP tells where to send them.
>
> -- glen

I was thinking to follow this implementation:

http://www.itee.uq.edu.au/~peters/xsvboard/stack/stack.htm

maybe upgrading it to a 10/100Mb Ethernet, but I changed idea. Anyway
they says they can handle arp send and arp request properly, but I
haven't tested it yet.

Bye

Dek

Dek wrote:
> I was thinking to follow this implementation:
> 
> http://www.itee.uq.edu.au/~peters/xsvboard/stack/stack.htm
great link but where are the VHDL source files ?

> Dek
yg

-- 
http://ygdes.com / http://yasep.org

whygee <y...@yg.yg> writes:

>Dek wrote:
>> I was thinking to follow this implementation:
>> 
>> http://www.itee.uq.edu.au/~peters/xsvboard/stack/stack.htm
>great link but where are the VHDL source files ?

>> Dek
>yg

>-- 
>http://ygdes.com / http://yasep.org

	on the project home page above that at in a zip file.

http://www.itee.uq.edu.au/~peters/xsvboard/index.html

Peter Van Epp

Peter Van Epp wrote:
>> great link but where are the VHDL source files ?
> 	on the project home page above that at in a zip file.
> http://www.itee.uq.edu.au/~peters/xsvboard/index.html
oh thanks again, I completely missed it :-/

> Peter Van Epp
yg

-- 
http://ygdes.com / http://yasep.org