Using QDRII  x18 in 2-burst mode, I assume that
the data/adr/cmd bus are all 
DDR signals using the same clock domain (except the read and write signal 
wich are single data rate)

The docs say there are limitations on where to put the data bus, and then I 
can put the adr/cmd on what is left in the bank. This appears to be a bit 
weird, as in this mode they are all clocked in at the same DDR(K clk) 
domain.

Trying to compile it with swapped pins does give an error like:
"Error: Can't place I/O "d[4]" to I/O location Pin_AG6 because it does not

support x18 mode memory interfaces"
AG6 is not in a x18 DQ bus, but its on the same bank as the other signals in 
the domain.

I wonder if anyone got experience with this. Is it just a lazy pinout guide 
that dates back from the modes where adr was single data rate? Or is there a 
hardware explanation?

Maybe there is a way to override the error message?

(Im clocking at half the max allowed, so there should be some overhead in 
timing)