I am not sure why the QuartusII synthesis tool is
considering
ReqInFifoDataIn[72] a latch and not a flip-flop?  ReqInFifoData[72] is
clearly defined as part of synchronous always block.  It is getting
used by wTag signal - Here I am anding the D input of the Flip-Flop
and Qn output of the same D flip-flop.  The purpose of this is to
generate one clock wide wTag pulse.

 input [81:0] RxStreamData0,

 wire wTag = RxStreamData0[72] & ~ReqInFifoDataIn[72];

 always @(posedge AppClk or negedge PcieRstN) begin
   if (!PcieRstN) begin
    ReqInFifoDataIn <= 96'b0;
    ReqInFifoDataValid <= 1'b0;
    ReqInFifoDataVal <= 1'b0;
    end
   else begin
    ReqInFifoDataIn[81:0] <= RxStreamData0[81:0];
    ReqInFifoDataValid <= RxStreamValid0;
    ReqInFifoDataVal <= ReqInFifoRd;
    end
 end

On Feb 12, 1:51=A0pm, Test01
<cpan...@yahoo.com> wrote:
> I am not sure why the QuartusII synthesis tool is considering
> ReqInFifoDataIn[72] a latch and not a flip-flop? =A0ReqInFifoData[72] is
> clearly defined as part of synchronous always block. =A0It is getting
> used by wTag signal - Here I am anding the D input of the Flip-Flop
> and Qn output of the same D flip-flop. =A0The purpose of this is to
> generate one clock wide wTag pulse.
>
> =A0input [81:0] RxStreamData0,
>
> =A0wire wTag =3D RxStreamData0[72] & ~ReqInFifoDataIn[72];
>
> =A0always @(posedge AppClk or negedge PcieRstN) begin
> =A0 =A0if (!PcieRstN) begin
> =A0 =A0 ReqInFifoDataIn <=3D 96'b0;
> =A0 =A0 ReqInFifoDataValid <=3D 1'b0;
> =A0 =A0 ReqInFifoDataVal <=3D 1'b0;
> =A0 =A0 end
> =A0 =A0else begin
> =A0 =A0 ReqInFifoDataIn[81:0] <=3D RxStreamData0[81:0];
> =A0 =A0 ReqInFifoDataValid <=3D RxStreamValid0;
> =A0 =A0 ReqInFifoDataVal <=3D ReqInFifoRd;
> =A0 =A0 end
> =A0end

I'm not that familiar with Quartus, but in Xilinx tools there
are often messages that reference "flip-flop/latch" which is
the cover-all-cases text to talk about a register.  The only
weird thing in your code is that RegInFifoDataIn would
appear to be 96 bits as evidenced by the reset term, but
only 82 bits are assigned in the clocked term.  That would
tend to make bits 82 and up "latches" but doesn't explain
the problem with bit 72.

Regards,
Gabor

On Fri, 12 Feb 2010 10:51:20 -0800 (PST), Test01
<c...@yahoo.com>
wrote:

>I am not sure why the QuartusII synthesis tool is considering
>ReqInFifoDataIn[72] a latch and not a flip-flop?  

Hollow and self-mocking laughter.... This is an example
of the error I make more than any other when writing 
RTL code.

>ReqInFifoData[72] is
>clearly defined as part of synchronous always block. 

No, it's not!  You do NOT write to ReqInFifoData[75:82]
in the clocked (else) part of the always block; it's
only written in the reset branch.  The clocked branch
writes only to the lower 82 bits.

It probably doesn't matter; if you don't use those
extra bits, their flip-flops will be removed by
synthesis optimizations.
-- 
Jonathan Bromley

Jonathan Bromley
<j...@mycompany.com> wrote:
(snip, someone wrote)
 
>>ReqInFifoData[72] is
>>clearly defined as part of synchronous always block. 
 
> No, it's not!  You do NOT write to ReqInFifoData[75:82]
> in the clocked (else) part of the always block; it's
> only written in the reset branch.  The clocked branch
> writes only to the lower 82 bits.

The usual rule in other newgroups is to post the declarations
of the data along with the code.  As we don't know the width
of RegInFifoData it is hard to say.  It does seem likely to
be ore than 82, though.
 
> It probably doesn't matter; if you don't use those
> extra bits, their flip-flops will be removed by
> synthesis optimizations.

-- glen

On Fri, 12 Feb 2010 22:46:31 +0000 (UTC), glen
herrmannsfeldt wrote:

>The usual rule in other newgroups is to post the declarations
>of the data along with the code. 

A good plan, for sure.  Maybe a declaration would have
helped me to write "[95:82]", which is what I meant,
instead of "[75:82]", which is what I wrote...

> As we don't know the width
>of RegInFifoData it is hard to say.  It does seem likely to
>be more than 82, though.

I took the line
  ReqInFifoData <= 96'b0;
to be a sufficiently broad hint :-)
-- 
Jonathan Bromley

Thanks for all the replies as it helped resolve
the issue.  I need to
be more precise in assignment statements.