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Comp.Arch.FPGA | VHDL vs Verilog
There are 39 messages in this thread.
You are currently looking at messages 0 to 10.
VHDL vs Verilog - whygee - 2010-02-12 19:15:00
hi, recently I read a quote about VHDL vs Verilog, along the lines of "VHDL is made by SW people who don't understand HW and vice versa"... Does anybody know the exact wording and origin ? yg -- http://ygdes.com / http://yasep.org______________________________
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Re: VHDL vs Verilog - Symon - 2010-02-12 20:16:00
On 2/13/2010 12:15 AM, whygee wrote: > hi, > > recently I read a quote about VHDL vs Verilog, > along the lines of "VHDL is made by SW people who > don't understand HW and vice versa"... > > Does anybody know the exact wording and origin ? > > yg FFS, don't we have enough wasted bandwidth bickering over bypass networks? Every hardware engineer _knows_ VHDL is better, but would rather kill their mother (if they knew who she was) than admit it. Now take your thinly disguised troll post and piss off... ...to comp.lang.vhdl where you will find polite software people. Ask for Jonathan, Mike and KJ. Tell them I sent you. With special love, Syms. xx p.s. http://www.googlefight.com/index.php?lang=en_GB&word1=vhdl&word2=verilog______________________________
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Re: VHDL vs Verilog - rickman - 2010-02-12 23:47:00
On Feb 12, 7:15=A0pm, whygee <y...@yg.yg> wrote: > hi, > > recently I read a quote about VHDL vs Verilog, > along the lines of "VHDL is made by SW people who > don't understand HW and vice versa"... > > Does anybody know the exact wording and origin ? > > yg > --http://ygdes.com/http://yasep.org Just ignore the troll. I'd like to get an answer to your question. Rick
Re: VHDL vs Verilog - KJ - 2010-02-13 00:22:00
On Feb 12, 8:16=A0pm, Symon <symon_bre...@hotmail.com> wrote: > ...to comp.lang.vhdl where you will find polite software people. Ask for > Jonathan, Mike and KJ. Tell them I sent you. > Ooooo...you read my posts and am on your recommended reading list now!!! KJ
Re: VHDL vs Verilog - whygee - 2010-02-13 00:25:00
hi ! Symon wrote: > FFS, don't we have enough wasted bandwidth bickering over bypass > networks? Every hardware engineer _knows_ VHDL is better, but would > rather kill their mother (if they knew who she was) than admit it. I have no shame to admit that I like VHDL (well, it's more a love/hate stuff, considering some aspects), but I know that Verilog exists, and I accept that others like it instead. The phrase that I partly remember summed up many things about the divergences between these two major HDL. > Now take your thinly disguised troll post and piss off... it's not a troll, it's an informal research for a paper. I just wanted to know where the humor I read somewhere (here ?) comes from. Is it attributed ? > ...to comp.lang.vhdl where you will find polite software people. does THAT exist ? > Ask for Jonathan, Mike and KJ. Tell them I sent you. hehe :-) no thanks, I post here because FPGA are not tied to one langage, so there are people here who know both HDLs. > With special love, Syms. xx hmmm "special love" is for tomorrow, feb.14th :-) > p.s. > > http://www.googlefight.com/index.php?lang=en_GB&word1=vhdl&word2=verilog well, that's not what I'm looking for. thanks for the off-topic anyway :-) yg -- http://ygdes.com / http://yasep.org______________________________
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Re: VHDL vs Verilog - whygee - 2010-02-13 00:29:00
KJ wrote: > On Feb 12, 8:16 pm, Symon <symon_bre...@hotmail.com> wrote: >> ...to comp.lang.vhdl where you will find polite software people. Ask for >> Jonathan, Mike and KJ. Tell them I sent you. > Ooooo...you read my posts and am on your recommended reading list now!!! I did not know that I would trigger so many strong reactions, you know, it's just a reference check for a paper, I have no intention to start a vi vs emacs^W^W^Wnother pointless flamewar. regards, > KJ yg -- http://ygdes.com / http://yasep.org______________________________
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Re: VHDL vs Verilog - 2010-02-13 04:15:00
whygee <y...@yg.yg> writes: > Does anybody know the exact wording and origin ? You mean this? http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4 Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?______________________________
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Re: VHDL vs Verilog - Jonathan Bromley - 2010-02-13 04:20:00
On Sat, 13 Feb 2010 10:15:34 +0100, Petter Gustad <n...@gustad.com> wrote: >whygee <y...@yg.yg> writes: > >> Does anybody know the exact wording and origin ? > >You mean this? > >http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4 Right, that's it, but the epithet has been around far longer than that post. -- Jonathan Bromley whose location in the three-dimensional space rude<->polite VHDL<->Veriiog software<->hardware continues to vary strongly as a function of weather, my employer's demands, what's cool, and other factors.______________________________
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Re: VHDL vs Verilog - Eric Smith - 2010-02-13 04:31:00
On Feb 12, 4:15=A0pm, whygee <y...@yg.yg> wrote: > recently I read a quote about VHDL vs Verilog, > along the lines of "VHDL is made by SW people who > don't understand HW and vice versa"... > > Does anybody know the exact wording and origin ? That's a quote by someone who doesn't understand VHDL.______________________________
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Re: VHDL vs Verilog - Jonathan Bromley - 2010-02-13 05:34:00
On Sat, 13 Feb 2010 06:29:20 +0100, whygee wrote: >I did not know that I would trigger so many strong reactions, <wipes spilt coffee from keyboard, resets cardiac pacemaker> Ignorance is bliss, but often unhelpful. -- Jonathan Bromley______________________________
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