After Symon's pleading to re-post, here it is...

>>>>>>>>>>>>>>>>>>>>>>&g
t;>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>
I'm about to start the layout on a board which I think needs
a 10 layer stack.

After the religious wars betwen rickman and Symon on decoupling I'm
unsure on the best stack but am veering towards...

1  signal - Top
2  GND plane
3  signal
4  signal
5  PWR plane
6  GND plane
7  signal
8  signal
9  PWR & GND plane
10 signal - Bottom
>>>>>>>>>>>>>>>>>>>>>>&g
t;>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>

I'll keep the gaps between layers 2 and 9 and the associated signal
layers fairly tight.

What I didn't say was that this application isn't terribly
demanding but it would be good to have a 'useful' stack defined
that I know can be built for the future.


Answering some of the previous comments...

Gabor:
> If you're planning a solid plane for the "PWR plane" on
> layer 5, I'd probably swap that one with layer 9 so you'd
> have a solid plane near the bottom.  Otherwise you need
> to be careful routing high speed signals across the plane
> splits on layers 8 and 10.

Understood, but in this application I can fairly easily route
any power in where there are not IO signals.


Symon:
> I've given up on that last thread, but I'm a
> glutton for religious wars, because when I win/martyr myself, my
> religion promises me a stripper factory and a beer volcano. It's gospel!

What's that, Plymouth Bretheren?


> you could make clear whether you are
> using a 1152 pin package because you want to use all the I/O or the
> reason is you need so much logic for your application that you need that
> big a package.

That's what's in the reqts spec (mix of amount of logic with reasonable
number of IO).

>  Are you gonna use any gigabit stuff to the BGA? If so, what rate?

No, fastest outputs are several 200MHz single ended clocks. These will
be kept short, source terminated and trace impedance tightly controlled.

The biggest concern is clock & PLL useage flexibility (system clock to
all PLL inputs) and optimal jitter performance on the 200MHz clock IOs.


> What are you connecting the 1152 pin part to?

I can't give too many details but it's a number of SDRAMs, FLASH, PCI
etc. Nothing madly fast but a few interfaces I'll need to be careful
with.

> Is the 1152 pin part an FPGA?

Yep, Stratix EP3SE100F1152

> How many supplies does the 1152 pin part need?

Not that many, I've maneged to keep the number down.


> What rise time are you shooting for on the I/O from this BGA?

As slow as possible. There are the 200MHz outputs above and a
synch ram which might be runat 167MHz but that's it.

> Nial, have you ever been in a Turkish prison?

Ahem, no comment.

> Is this board going to be sold? In a metal box? Does it need CE
> approval or somesuch?

No, no, no.

> How much time/money have you got?

Not enough as usual.

> Do you do layout yourself?

Yes, I've done several BGAs, this is the first that needs 10 layers.
I'm using Altium Designer so matching trace lengths etc if easy
enough.

I'm away back to Belfast tomorrow (it's half term) so might not be able
to reply to any comments for a while.




Nial

On Feb 15, 7:34 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> After Symon's pleading to re-post, here it is...
>
>
>
> I'm about to start the layout on a board which I think needs
> a 10 layer stack.
>
> After the religious wars betwen rickman and Symon on decoupling I'm
> unsure on the best stack but am veering towards...
>
> 1  signal - Top
> 2  GND plane
> 3  signal
> 4  signal
> 5  PWR plane
> 6  GND plane
> 7  signal
> 8  signal
> 9  PWR & GND plane
> 10 signal - Bottom

Rather than have us tell you what we think of your design and ideas
(which you actually don't give much of) why not you tell us why you
want to do things the way you are doing them.  I think it would be
much more useful to discuss the rational rather than the result.
There are any number of reasons to do something one way or another
which may or may not have been stated.  Since we can't easily know all
the facts, it might be easier for us to critique your thinking rather
than your result.


> I'll keep the gaps between layers 2 and 9 and the associated signal
> layers fairly tight.

Here is an example.  Why are you concerned about layers 2 and 9 and
not 5 and 6?  Why are you concerned about spacing rather than coupling
or impedance?  My point is that the spacing of signal layers to power
planes can vary depending on a number of factors including limitations
in the stackup total thickness.  What is mostly important is the ratio
of the spacing to the trace width (which is also how you control
impedance).


> What I didn't say was that this application isn't terribly
> demanding but it would be good to have a 'useful' stack defined
> that I know can be built for the future.
>
> Answering some of the previous comments...
>
> Gabor:
>
> > If you're planning a solid plane for the "PWR plane" on
> > layer 5, I'd probably swap that one with layer 9 so you'd
> > have a solid plane near the bottom.  Otherwise you need
> > to be careful routing high speed signals across the plane
> > splits on layers 8 and 10.
>
> Understood, but in this application I can fairly easily route
> any power in where there are not IO signals.

I'm not clear on what you are saying.  Are you suggesting that you
will be routing power on signal layers?  What I'm really curious about
is why you want to mix power and ground on one plane.  Everything I
have learned says that coupled power and ground planes are the same
for high speed signals and you will get better coupling if you have
more area common between the ground and power planes.  So using the
entire layer for power should give better coupling and better high
speed signal returns.  If you don't have good high frequency coupling
between power and ground, won't you see a change in impedance if a
trace on an adjacent signal layer passes from the ground area to the
power area and vice versa?

In other words, I don't get why you are mixing ground and power on one
plane when you already have two ground planes.


> Symon:
>
> >  Are you gonna use any gigabit stuff to the BGA? If so, what rate?
>
> No, fastest outputs are several 200MHz single ended clocks. These will
> be kept short, source terminated and trace impedance tightly controlled.

With the stackup shown above I suggest that you keep them off of
layers 7, 8 and 10.  Potentially poor impedance control depending on
the area and spacing of your power planes on layer 9.


> The biggest concern is clock & PLL useage flexibility (system clock to
> all PLL inputs) and optimal jitter performance on the 200MHz clock IOs.
>
> > What are you connecting the 1152 pin part to?
>
> I can't give too many details but it's a number of SDRAMs, FLASH, PCI
> etc. Nothing madly fast but a few interfaces I'll need to be careful
> with.
>
> > Is the 1152 pin part an FPGA?
>
> Yep, Stratix EP3SE100F1152
>
> > How many supplies does the 1152 pin part need?
>
> Not that many, I've maneged to keep the number down.

I've heard of primitive number systems that count 1, 2, 3 and "more
than 3".  But I've not heard of one that used "Not that many".  Can
you tell us if you are using 1, 2, 3 or "more than 3" power supply
voltages?   ;^)


> > What rise time are you shooting for on the I/O from this BGA?
>
> As slow as possible. There are the 200MHz outputs above and a
> synch ram which might be runat 167MHz but that's it.

So how slow is that?  With the huge number of I/Os you appear to be
using, SSN (simultaneous switching noise) is potentially large.  You
might want to simulate that to get an idea of the amount of ground
bounce you will see.  And when you do it, I recommend that you
simulate *all* of the components in your PDS, not just one example
component... ;^)

It has occurred to me that Altera must have done simulations on their
parts to be sure that they are usable with a large number of I/Os
switching.  You might want to ask them for info on their simulations.
They may have detailed simulations available complete with recommended
stackups and PDS specs.  If they have done a worst case design
analysis, maybe you won't have to reinvent the wheel.  It's worth
asking about.

Rick

If its any help I can relate my experience of
designing an 8 layer PCIExpress card (4 lanes). This consisted of a Virtex 5 with four DDR2 SDRAMcomponents operating at 333 MHz. The stackup I used :-

1. Signal
2. Gnd
3. Signal
4. Pwr (1V8 2V5 1V0(GTP))
5. Pwr (1V0 0V9 1V2 (GTP))
6. Signal
7. Pwr (3V3)
8. Signal

I tried to keep one continous plane (layers 2 and 7) next to each signallayer for controlled impedance routing. I followed the Xilinx documentationwith regard to decoupling caps and power supply requiremnts. I routed theGTP signals on layers 1 and 8 next to the continuous planes. The DDR2signals were kept as short as possible (about 50mm max). I have no externaltermination on the tracks; I use the Xilinx DCI which works very well. Idid do some simulations using Hyperlynx before starting the board to verifythere would be no problem. I have to say that the board has workedperfectly from the start of testing so I guess I must have done somethingright.

Jon  	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hi Nial,

OK, I understand your reticence to blab too much about your board, I 
would do the same.

FWIW, if I was gonna do this board at 1.6 mm thickness I would start from:-

1 Signal
2 Signal
3 Ground
4 Power pours, rarely some slow signals if absolutely needed.
****Thick core, 25 mils or so.****
5 Power pours, rarely some slow signals if absolutely needed.
6 Ground
7 Signal
8 Signal


To be able to route this up, I would use "frickin' laser beam" drilled 
microvias between layers 1 & 2, and maybe 7 & 8 if I needed it on a 
congested board. I'd try not to use the I/O balls in the middle of the 
package, if I could help it. This assumes the BGA is mounted on layer 1. 
The micro-vias can be 'in pad'. I would use 0.1mm-0.1mm-0.1mm 
track-gap-track. I use 1oz copper for everything, good for heat 
transfer. I would think long and hard about the signal assignments on 
the FPGA to ease the routing. I know Philip uses Altium and he was 
singing its praises when I last saw him; I was impressed with what it 
could do wrt pin swapping.

I've used this approach on several boards, a few with 1152 BGAs, with 
small sections of 11G stuff, with multiple different Vccos on the same 
part, DDR-2 DIMMs and 3G MGT stuff.

I can't be arsed to justify this on usenet, so, I'm not proselytising 
anything to you, because I don't know what your specific requirements 
are. I offer it as food for thought for you and your PCB vendor.

If you are interested, you can google my name and microvias and see what 
I've posted here in the past. Somewhere you'll find a link to a picture 
of a board I did long ago that Philip is still hosting I think.

Also, here's some reading material about some specific issues with big 
fast power hungry FPGAs:-

http://www.xilinx.com/support/documentation/application_notes/xapp689.pdf
I notice the Altera parts have much less I/O pin capacitance, 4pF vs 
10pF, so this should help you wrt ground bounce.

http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
Have Altera sorted out their ball positions on Stratix 3? I couldn't 
find a nice picture.

Good luck, Syms.

p.s. I see no reason why Jon's suggested stack up wouldn't work either, 
unless it runs out of routing channels with only four signal layers and 
through vias.