Hi, I'm workng with MGT as GT_CUSTOM.
I use the MGT for transmiting to pulses of .66ns(1/15Ghg).
I check all the delays with FPGA editor and all was ok, but I mesure thepulses at the SATA conector and there are a delay between SATA0 and SATA1of 500ps.
I simplified the program as much as posible and this delay is alwayspresent.
The mesurment was made with the same cable lenght.

Same ideas?
Thansk
Marcelo



	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On 2/15/2010 10:08 PM, msegura wrote:
> Hi, I'm workng with MGT as GT_CUSTOM.
> I use the MGT for transmiting to pulses of .66ns(1/15Ghg).
> I check all the delays with FPGA editor and all was ok, but I mesure the
> pulses at the SATA conector and there are a delay between SATA0 and SATA1
> of 500ps.

What are these two signals? Where do they connect to your FPGA?

Syms.

On Feb 15, 2:08=A0pm, "msegura"
<ms_...@usc.edu> wrote:
> Hi, I'm workng with MGT as GT_CUSTOM.
> I use the MGT for transmiting to pulses of .66ns(1/15Ghg).
> I check all the delays with FPGA editor and all was ok, but I mesure the
> pulses at the SATA conector and there are a delay between SATA0 and SATA1
> of 500ps.
> I simplified the program as much as posible and this delay is always
> present.
> The mesurment was made with the same cable lenght.
>
> Same ideas?
> Thansk
> Marcelo
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

The lane-to-lane skew isn't zero and the maximum value is listed in
the device datasheet. For instance with Virtex-5 the GTP value is
855ps.

Ed McGettigan
--
Xilinx Inc.

Ed, So you told me that its no posible to sent two bits using diferent MGT with the same
delay?But how work the comm systems that use several paralle channels?I'll check the datasheet for my virtex2p.Marcelo

---
frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

On Fri, 19 Feb 2010 13:58:25 -0600, Marcelo
<u...@compgroups.net/>
wrote:

>Ed, 
>So you told me that its no posible to sent two bits using diferent MGT with the same
delay?
>But how work the comm systems that use several paralle channels?

Inter-lane skew is handled in the controller during training. Transmit
skew is not the only cause of skew, channel (cable or pcb) and
receivers also contribute to it too. It's much easier to manage it in
digital domain after data recovery than to try to make perfect
channels.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

On 2/19/2010 7:58 PM, Marcelo wrote:
> Ed,
> So you told me that its no posible to sent two bits using diferent MGT with the same
delay?
> But how work the comm systems that use several paralle channels?

http://en.wikipedia.org/wiki/XAUI

yes I understand but 500ps is to much for pcb
delay, are 15cm.The idia is ti desing an ultra wideband transmiter using the MGT.I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo
pulse), must be the same.

---
frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

On Feb 19, 11:58=A0am, Marcelo
<u...@compgroups.net/> wrote:
> Ed,
> So you told me that its no posible to sent two bits using diferent MGT wi=
th the same delay?
> But how work the comm systems that use several paralle channels?
> I'll check the datasheet for my virtex2p.
> Marcelo
>
> ---
> frmsrcurl:http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-=
sata0-...

For interfaces that use multiple MGTs, such as PCIe and XAUI, the
protocol uses channel bonding that allows the receiver to align the
data correctly with multiple (1-40+) bits of skew.  The are some
standards that want to skimp on the logic resources needed to
implement channel bonding and have a tighter requirement on the lane
skew, but the protocols that I am aware of still allow for about
1000pS of lane skew.

Expecting 0pS of lane skew is not realistic.

Ed McGettigan
--
Xilinx Inc.

On 2/22/2010 2:03 AM, marcelo wrote:
> yes I understand but 500ps is to much for pcb delay, are 15cm.
> The idia is ti desing an ultra wideband transmiter using the MGT.
> I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo
pulse), must be the same.
>
>
> ---
> frmsrcurl:
http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Do you remember this reply from a week ago?


"What are these two signals? Where do they connect to your FPGA?"


Why don't you answer it?

Symon.

On 2/22/2010 10:18 AM, Symon wrote:
> On 2/22/2010 2:03 AM, marcelo wrote:
>> yes I understand but 500ps is to much for pcb delay, are 15cm.
>> The idia is ti desing an ultra wideband transmiter using the MGT.
>> I'm using BPKS modulation, so the delay between TX1(positive pulse)
>> and TX2(negativo pulse), must be the same.
>>
>>
>> ---
>> frmsrcurl:
>> http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1
>>
>
> Do you remember this reply from a week ago?
>
>
> "What are these two signals? Where do they connect to your FPGA?"
>
>
> Why don't you answer it?
>
> Symon.

Sorry, ignore that. I thought you were the OP. FWIW, the P and N signals 
will be aligned to within a few ps. Different lanes will not be.

HTH,

Syms.