Hello !

I have a very big problem. I created a simple procesor and on simulation itworks fine, on step mode it works fine but when it is running on full speedof clock it got crazy... :( It should execute instruction i order0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and itexecutes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 or0.1 or sometimes it is as it should. Sometimes it stops suddenly executingor executing too much. It is written in VHDL on Spartan 3A. It is too bigto show it here but maybe some experts will be able to tell me what isgoing on... I have constraints like this in UCF file :

NET "Clock" LOC = C10;
NET "Clock" IOSTANDARD = LVCMOS33;
NET "Clock" PERIOD = 62.5ns HIGH 50%;
NET "Reset" LOC = H4;
NET "Reset" IOSTANDARD = LVCMOS33;
NET "TX" LOC = B3;
NET "TX" IOSTANDARD = LVCMOS33;
NET "RX" LOC = A3;
NET "RX" IOSTANDARD = LVCMOS33;

are there any other constraint useful for me ? Can it be constraint fault ?Or  it must be design problem ? Or something else ? 16Mhz clock isconnected to FPGA. It works OK using step by step mode but on full speedit's stragne bevahior... I really need help, I trying to solve it for threedays and nothing...

Thank you all for any answers...	   
					
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On 2/17/2010 11:55 PM, de4 wrote:
> works fine, on step mode it works fine but when it is running on full speed
> of clock it got crazy...

> NET "Clock" PERIOD = 62.5ns HIGH 50%;
>

What is 'step mode' exactly? Your clock is relatively slow. So, your 
problem is probably something to do with clock skew. Is your clock on a 
GBUF? Does your clock connect to anything other than a dedicated clock 
input of the FPGAs innards?

HTH Syms.

On Feb 17, 3:55=A0pm, "de4"
<de4@n_o_s_p_a_m.poczta.onet.pl> wrote:
> Hello !
>
> I have a very big problem. I created a simple procesor and on simulation =
it
> works fine, on step mode it works fine but when it is running on full spe=
ed
> of clock it got crazy... :( It should execute instruction i order
> 0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it
> executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 =
or
> 0.1 or sometimes it is as it should. Sometimes it stops suddenly executin=
g
> or executing too much. It is written in VHDL on Spartan 3A. It is too big
> to show it here but maybe some experts will be able to tell me what is
> going on... I have constraints like this in UCF file :
>
> NET "Clock" LOC =3D C10;
> NET "Clock" IOSTANDARD =3D LVCMOS33;
> NET "Clock" PERIOD =3D 62.5ns HIGH 50%;
> NET "Reset" LOC =3D H4;
> NET "Reset" IOSTANDARD =3D LVCMOS33;
> NET "TX" LOC =3D B3;
> NET "TX" IOSTANDARD =3D LVCMOS33;
> NET "RX" LOC =3D A3;
> NET "RX" IOSTANDARD =3D LVCMOS33;
>
> are there any other constraint useful for me ? Can it be constraint fault=
 ?
> Or =A0it must be design problem ? Or something else ? 16Mhz clock is
> connected to FPGA. It works OK using step by step mode but on full speed
> it's stragne bevahior... I really need help, I trying to solve it for thr=
ee
> days and nothing...
>
> Thank you all for any answers... =A0 =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

You don't mention if the design passes P&R with no timing errors.
Simply specifying constraints
doesn't mean they are actually met.

John Providenza

I'm bigginner so I was trying to verify if my
work actually works in FPGA.
So as clock of whole system I used FSM controled by push button. When Ipush the button it gave one clock cycle and because that processor gone tonext state - this is what I meant saying 'step mode'. I have writtensoftware that reads all registers and memory and sending do computer. Andthere everything looks ok...

Sorry but I don;t know what is GBUF ? I will find it out...
My clock isn't comnected to anything else then to FPGA ( I have AvnetSparatan 3A board)

And about constraints in Map messages I have only : (only infos)

MapLib:562 - No environment variables are currently set.

MapLib:159 - Net Timing constraints on signal Clock are pushed forwardthrough input buffer.

LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single endedoutputs can be dramatically reduced by designating them as fast outputs.

It doesn't tell me a lot :(

Timing messages 

Timing:2752 - To get complete path coverage, use the unconstrained pathsoption. All paths that are not constrained will be reported in theunconstrained paths section(s) of the report.

Timing:3339 - The clock-to-out numbers in this timing report are based on a50 Ohm transmission line loading model.  For the details of this model, andfor more information on accounting for different loading conditions, pleasesee the device datasheet.

And in detailed Post-PAR Static Timing Report is written 
All constraints were met.

What Can I check more ?	   
					
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On Wed, 17 Feb 2010 17:55:07 -0600,
"de4" <de4@n_o_s_p_a_m.poczta.onet.pl>
wrote:

>Hello !
>
>I have a very big problem. I created a simple procesor and on simulation it
>works fine, on step mode it works fine but when it is running on full speed
>of clock it got crazy... :

>are there any other constraint useful for me ? Can it be constraint fault ?
>Or  it must be design problem ? Or something else ? 16Mhz clock is
>connected to FPGA. 

16MHz is slow enough that problems meeting timing are unlikely.

Is the processor accessing any memory external to the FPGA, or just thu internal
BRAMs? External memory is a likely source of timing problems.

Check for any inputs to the processor that aren't themselves clocked by the same
clock, and eliminate them (by reclocking them from the CPU clock.

- Brian

>On Wed, 17 Feb 2010 17:55:07 -0600,
"de4"
<de4@n_o_s_p_a_m.poczta.onet.pl>
>wrote:
>
>>Hello !
>>
>>I have a very big problem. I created a simple procesor and on simulation
it
>>works fine, on step mode it works fine but when it is running on full
speed
>>of clock it got crazy... :
>
>>are there any other constraint useful for me ? Can it be constraint fault
?
>>Or  it must be design problem ? Or something else ? 16Mhz clock is
>>connected to FPGA. 
>
>16MHz is slow enough that problems meeting timing are unlikely.
>
>Is the processor accessing any memory external to the FPGA, or just thu
internal
>BRAMs? External memory is a likely source of timing problems.
>
>Check for any inputs to the processor that aren't themselves clocked by
the same
>clock, and eliminate them (by reclocking them from the CPU clock.
>
>- Brian
>


Thank you for response...

Processor don't accessing external memory only BlockRAM based RAM.
I have one input in my system that is a clock connected to global clock.
this input is (clock signal) connected to processor, ram and I/O ( uses TX
and RX line to communicate with processor from outside). Processor is
connected with Clock, Reset and RAM signals. RAM is connected with Clock,
Processor and to I/O unit (dual port). To I/O unit is connected clock,
Reset and signal from ram and TX,RX lines. 

I writing because it is strage behavior I even could say that it is
randomly...
If something would be wrongly design (I mean some fsm in control unit)
program would be executed badly but always in the same way... In my case
some times is 
PC values are 0, 1 ,2 ,4, 5 some times it is 0, 1 and stops. 
16 Mhz is not too much...

Best regards,
Maciek


	   
					
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On 2/18/2010 12:12 PM, de4 wrote:
>
> I writing because it is strage behavior I even could say that it is
> randomly...
> If something would be wrongly design (I mean some fsm in control unit)
> program would be executed badly but always in the same way... In my case
> some times is
> PC values are 0, 1 ,2 ,4, 5 some times it is 0, 1 and stops.
> 16 Mhz is not too much...
>
> Best regards,
> Maciek
>
Hi Maciek,
Can you use chipscope to look at the signals which control the program 
counter, and the PC's value?
Do you get any warnings from P&R something like "Warning: Signal clock 
connects to non-clock resource"?

Look in all the report files for any warnings to do with your clock signal.

Does your reset get released synchronously to the clock?

HTH, Syms.

>Hi Maciek,
>Can you use chipscope to look at the signals which control the program 
>counter, and the PC's value?
>Do you get any warnings from P&R something like "Warning: Signal clock 
>connects to non-clock resource"?
>
>Look in all the report files for any warnings to do with your clocksignal.
>
>Does your reset get released synchronously to the clock?
>
>HTH, Syms.
>

Chipscope is beyond my possibilities... I program FPGA using Avnet Programmand I don't have Platform Cable... In PAR I don't have any warnings atall...
I will search them but I didn't see any warnings.

Sorry but "Does your reset get released synchronously to the clock?"
I don;t understand this - I have some Dff like this :

entity D_FF is
	port(	D, Clock, Reset		: in STD_LOGIC;
				Q, notQ 				: out STD_LOGIC);
end D_FF;

architecture CPU of D_FF is
signal Qout : STD_LOGIC;
begin

		PROCESS(D, Clock, Reset)
		BEGIN
			IF Reset = '1' THEN -- Don’t wait for clock
				Q <= '0';
				notQ <= '1';
			ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge
				Q <= D;
				notQ <= not D;
		END IF;
		END PROCESS;

end CPU;


and this reset is connected to button on a board...
So I think rather not...

Thank you for response...	   
					
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On 2/18/2010 1:11 PM, de4 wrote:
>>
> 		PROCESS(D, Clock, Reset)
> 		BEGIN
> 			IF Reset = '1' THEN -- Don’t wait for clock
> 				Q<= '0';
> 				notQ<= '1';
> 			ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge
> 				Q<= D;
> 				notQ<= not D;
> 		END IF;
> 		END PROCESS;
>
> end CPU;
>
>
> and this reset is connected to button on a board...
> So I think rather not...
>
Hi,
So, it probably isn't the problem, but why is 'D' in your sensitivity list?

You should build a debounce circuit for the reset button that is 
synchronous to your clock.

http://en.wikipedia.org/wiki/Switch#Contact_bounce

HTH., Syms.

Also

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf