Hi,

I have a V4 with input clock frequency running at 130MHz. This clock
goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
named as "derived_clock" by Synplify. Now the timing report on the
input 130MHz is fine (positive slack) but the derived_clock doesn't
meet timing. How to contrain that?

Thanks.

You need to post your code so we can see how you
have coded the DCM.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Feb 18, 2:21=A0am, "maxascent"
<maxascent@n_o_s_p_a_m.yahoo.co.uk>
wrote:
> You need to post your code so we can see how you have coded the DCM.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Here is it, thanks.

 DCM_1 : DCM_ADV
        generic map(
            CLK_FEEDBACK          =3D> "1X",
            CLKDV_DIVIDE          =3D> 2.0,
            CLKFX_DIVIDE          =3D> 1,
            CLKFX_MULTIPLY        =3D> 2,
            CLKIN_DIVIDE_BY_2     =3D> FALSE,
            CLKIN_PERIOD          =3D> 7.6921,     -- 7.69 for 130MHz
            CLKOUT_PHASE_SHIFT    =3D> "NONE",
            DCM_PERFORMANCE_MODE  =3D> "MAX_SPEED",
            DESKEW_ADJUST         =3D> "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE    =3D> "LOW",
            DLL_FREQUENCY_MODE    =3D> "LOW",
            DUTY_CYCLE_CORRECTION =3D> TRUE,
            PHASE_SHIFT           =3D> 0,
            STARTUP_WAIT          =3D> FALSE
            )
        port map (
            CLK0     =3D> SClkPre,      -- *****violation here
            CLK180   =3D> open,
            CLK270   =3D> open,
            CLK2X    =3D> open,
            CLK2X180 =3D> open,
            CLK90    =3D> open,
            CLKDV    =3D> open,
            CLKFX    =3D> open,
            CLKFX180 =3D> open,
            DO       =3D> open,
            DRDY     =3D> open,
            LOCKED   =3D> DLL_LOCKED,
            PSDONE   =3D> open,
            CLKFB    =3D> SClk,
            CLKIN    =3D> SClkIn,
            DADDR    =3D> "0000000",
            DCLK     =3D> '0',
            DEN      =3D> '0',
            DI       =3D> "0000000000000000",
            DWE      =3D> '0',
            PSCLK    =3D> '0',
            PSEN     =3D> '0',
            PSINCDEC =3D> '0',
            RST      =3D> MasterRst
            );

Verictor pisze:
> Hi,
> 
> I have a V4 with input clock frequency running at 130MHz. This clock
> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
> named as "derived_clock" by Synplify. Now the timing report on the
> input 130MHz is fine (positive slack) but the derived_clock doesn't
> meet timing. How to contrain that?
> 
> Thanks.

Hi,

If incoming (external ) clock is used only to drive DCM, you have 
problem with your design. In different words your logic is too slow.
Anyway you can find everything in timing report. I don't know xilinx 
tools to well but clock coming from DCM should be constrained 
automatically. Correct me if I'm wrong

Adam

>Verictor pisze:
>> Hi,
>> 
>> I have a V4 with input clock frequency running at 130MHz. This clock
>> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
>> named as "derived_clock" by Synplify. Now the timing report on the
>> input 130MHz is fine (positive slack) but the derived_clock doesn't
>> meet timing. How to contrain that?
>> 
>> Thanks.
>

You havent added any clock buffers (BUFG) on the output of the DCM.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Feb 18, 12:51=A0pm, "maxascent"
<maxascent@n_o_s_p_a_m.yahoo.co.uk>
wrote:
> >Verictor pisze:
> >> Hi,
>
> >> I have a V4 with input clock frequency running at 130MHz. This clock
> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
> >> named as "derived_clock" by Synplify. Now the timing report on
the
> >> input 130MHz is fine (positive slack) but the derived_clock doesn't
> >> meet timing. How to contrain that?
>
> >> Thanks.
>
> You havent added any clock buffers (BUFG) on the output of the DCM.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

No, I do have inserted IBUFG to input clock and BUFG to the output of
the DCM. Just not shown on my post.

You should only need to specify the clock into
the DCM in the Synplifyconstraint file. If your design is not meeting timing then you need to lookin the Synplify report and find the problem.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Thu, 18 Feb 2010 17:18:14 -0800 (PST),
Verictor <s...@gmail.com> wrote:

>On Feb 18, 12:51 pm, "maxascent" <maxascent@n_o_s_p_a_m.yahoo.co.uk>
>wrote:
>> >Verictor pisze:
>> >> Hi,
>>
>> >> I have a V4 with input clock frequency running at 130MHz. This clock
>> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
>> >> named as "derived_clock" by Synplify. Now the timing report on
the
>> >> input 130MHz is fine (positive slack) but the derived_clock doesn't
>> >> meet timing. How to contrain that?
>>
>> >> Thanks.
>>
>> You havent added any clock buffers (BUFG) on the output of the DCM.
>>
>> Jon        
>>
>> ---------------------------------------        
>> Posted throughhttp://www.FPGARelated.com
>
>No, I do have inserted IBUFG to input clock and BUFG to the output of
>the DCM. Just not shown on my post.

Then we have to guess that the BUFG has SClkPre as input and SClk as output,
since SClk is taken to ClkFB (feedback) on the DCM.

Then SClk should be correctly aligned with the DCM input clock, which means
there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal).
Is that what you are observing?

- Brian

On Feb 19, 4:22=A0am, Brian Drummond
<brian_drumm...@btconnect.com>
wrote:
> On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...@gmail.com> w=
rote:
> >On Feb 18, 12:51=A0pm, "maxascent"
<maxascent@n_o_s_p_a_m.yahoo.co.uk>
> >wrote:
> >> >Verictor pisze:
> >> >> Hi,
>
> >> >> I have a V4 with input clock frequency running at 130MHz. This
cloc=
k
> >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
> >> >> named as "derived_clock" by Synplify. Now the timing
report on the
> >> >> input 130MHz is fine (positive slack) but the derived_clock
doesn't
> >> >> meet timing. How to contrain that?
>
> >> >> Thanks.
>
> >> You havent added any clock buffers (BUFG) on the output of the DCM.
>
> >> Jon =A0 =A0 =A0 =A0
>
> >> --------------------------------------- =A0 =A0 =A0 =A0
> >> Posted throughhttp://www.FPGARelated.com
>
> >No, I do have inserted IBUFG to input clock and BUFG to the output of
> >the DCM. Just not shown on my post.
>
> Then we have to guess that the BUFG has SClkPre as input and SClk as outp=
ut,
> since SClk is taken to ClkFB (feedback) on the DCM.
>
> Then SClk should be correctly aligned with the DCM input clock, which mea=
ns
> there will be several ns skew (=3D the BUFG delay) on SClkPre (the DCM0 s=
ignal).
> Is that what you are observing?
>
> - Brian- Hide quoted text -
>
> - Show quoted text -

Brian,

Your guess of BUFG is exactly right. Also yes, SClk should be aligned
with CLKIN, as you pointed out. When you said "observing", I think you
mean post-layout simulation? I haven't done that. But I think the
alignment should be ok.

Thanks,

On Tue, 23 Feb 2010 06:53:08 -0800 (PST),
Verictor <s...@gmail.com> wrote:

>On Feb 19, 4:22 am, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:
>> On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...@gmail.com>
wrote:
>> >On Feb 18, 12:51 pm, "maxascent"
<maxascent@n_o_s_p_a_m.yahoo.co.uk>
>> >wrote:
>> >> >Verictor pisze:
>> >> >> Hi,
>>
>> >> >> I have a V4 with input clock frequency running at 130MHz. This
clock
>> >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net
is
>> >> >> named as "derived_clock" by Synplify. Now the timing
report on the
>> >> >> input 130MHz is fine (positive slack) but the derived_clock
doesn't
>> >> >> meet timing. How to contrain that?
>>

>> >> You havent added any clock buffers (BUFG) on the output of the DCM.

>> >No, I do have inserted IBUFG to input clock and BUFG to the output of
>> >the DCM. Just not shown on my post.

>> Then SClk should be correctly aligned with the DCM input clock, which means
>> there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal).
>> Is that what you are observing?

>Your guess of BUFG is exactly right. Also yes, SClk should be aligned
>with CLKIN, as you pointed out. When you said "observing", I think you
>mean post-layout simulation? I haven't done that. But I think the
>alignment should be ok.

I actually meant "observing" because you observed in your original query,  you
reported the "derived clock" DCM0 signal (skewed as above) didn't meet timing.

Since the skew is expected, the question is, what exactly doesn't meet timing?

If there is any logic clocked off DCM0 it will probably not meet timing; but
there shouldn't be any. DCM0 should only connect to the BUFG and nothing else.

- Brian