Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | Question about altera root-port for Stratix4GX Hard IP


There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

Question about altera root-port for Stratix4GX Hard IP - Test01 - 2010-02-20 21:51:00

I have a question about Altera Stratix4GX PCIe Hard IP root port
question.  As per my understanding, the back end of the root-port
supports Avalon ST Bus thorugh which I can feed TLPs to pass
transactions downstream using the Hard IP root port.  Is it possible
to put it in a mode where all the transactions are passed on
downstream - even the PCI conig cycles?