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Comp.Arch.FPGA | Xilinx iodelay
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Xilinx iodelay - Chris Maryan - 2010-02-24 17:21:00
Intuitively, the iodelay found in Xilinx parts should be just a tapped delay line. But the need for a reference clock at a precise frequency indicates otherwise. Does anyone have any insight into how these are implemented? I'm not looking for an exact answer, but any reasonable explanation would be appreciated. The only idea I had is that it's a chain of FFs driven on a very fast clock (ref clk multiplied up to give 75ns taps ~13GHz) which seems very improbable). Any thoughts? Thanks, Chris______________________________
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Re: Xilinx iodelay - John McCaskill - 2010-02-24 17:41:00
On Feb 24, 4:21=A0pm, Chris Maryan <kmar...@gmail.com> wrote: > Intuitively, the iodelay found in Xilinx parts should be just a tapped > delay line. Yes, that is what it is. > But the need for a reference clock at a precise frequency > indicates otherwise. Does anyone have any insight into how these are > implemented? The reference clock is used to calibrate the tapped delay line so that it has a consistent delay that is resistant to changes in process, voltage and temperature. > > I'm not looking for an exact answer, but any reasonable explanation > would be appreciated. The only idea I had is that it's a chain of FFs > driven on a very fast clock (ref clk multiplied up to give 75ns taps > ~13GHz) which seems very improbable). > > Any thoughts? > > Thanks, > > Chris Regards, John McCaskill www.FasterTechnology.com