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Comp.Arch.FPGA | Spice simulation of IBIS details - model examples

There are 12 messages in this thread.

You are currently looking at messages 10 to 12.

Re: Spice simulation of IBIS details - model examples - rickman - 2010-03-02 08:07:00

On Mar 2, 1:08=A0am, -jg
<jim.granvi...@gmail.com> wrote:
> On Mar 2, 6:15=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > I'm talking about the boards. =A0I get virtually no ringing with the
> > slower edge rates. =A0The fastest, 20 mA/FAST, setting gives pronounced
> > ringing and 16 mA has some as well. =A0They are both 2 ns or less rise
> > times. =A0At 12 ns the ringing is gone and I only see the tiny notch in
> > the rising edge that I am convinced is not ringing or reflection.
>
> It depends on your terminology.
> The notch I mention below, I would call ringing, as it
> comes from a LCR+Slope model. It is effectively ringing summed onto
> the slowish rise time, and is not huge, but large enough to see a
> slight reverse in voltage.
>
> > BTW, a transmission line does not ring. =A0You can get reflections, but
> > unless there is some sort of feedback in your IO driver that is
> > oscillating, you won't see true ringing with a transmission line...
> > unless there is something with transmission lines that I didn't
> > learn. =A0It is often that reflections look like ringing because they
> > echo several times at lower amplitude each time around. =A0No?
>
> > Rick
>
> Just for fun, I added some guestimate numbers from what you said, and
> added a probe to the driving end, and voila, guess what?
>
> A small notch appears, on the driving end ;)
>
> Which end were you probing, your end, or connector, or the customers
> FPGA pin ?
>
> -jg

The driver.  Does it show up at the same time for both 8 and 12 mA
drive?

Rick



Re: Spice simulation of IBIS details - model examples - -jg - 2010-03-02 14:25:00

On Mar 3, 2:07=A0am, rickman
<gnu...@gmail.com> wrote:
> On Mar 2, 1:08=A0am, -jg <jim.granvi...@gmail.com> > > A small notch
appe=
ars, on the driving end ;)
>
> > Which end were you probing, your end, or connector, or the customers
> > FPGA pin ?
>
> > -jg
>
> The driver. =A0Does it show up at the same time for both 8 and 12 mA
> drive?

 That would be by varying the slew rate in the PWL source, and yes, it
comes and goes as the slew rate hits a critical threshold.

 Spice says the waveform at the receive end does not have that notch.

-jg

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