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Hi all,

I'm designing an LPDDR2 SDRAM memory interface controller for a
Virtex-6 FPGA based on the DDR3 interface controller provided by MIG
3.3.

The memory interface signals need a 1.2V IOStandard. For the single-
ended signals, either LVCMOS12 or HSTL_I_12 IOStandard can be used.
The problem is on the differential (CK and DQS) signals, there is no
differential 1.2V IOStandard supported. Is there any workaround for
this issue? Is it possible to configure the logic to a 1.5V IOStandard
(for example DIFF_SSTL15) and tweak VCCO and VREF in such a way to get
the IOB lines within the desired 1.2V swing?

Regards,
Shant

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