I'm trying to use bidirectional pins in Quartus
with Verilog. 
What's the correct way to do it? Altera has some example code:

http://www.altera.com/support/examples/verilog/ver_bidirec.html

But I don't really understand it. For example, it says it can 
drive the value b out but I can't see bidir being assigned to at 
all, rather just being connected to a when oe is asserted.

On Mar 3, 2:33=A0pm, Giorgos Tzampanakis
<g...@hw.ac.uk> wrote:
> I'm trying to use bidirectional pins in Quartus with Verilog.
> What's the correct way to do it? Altera has some example code:
>
> http://www.altera.com/support/examples/verilog/ver_bidirec.html
>
> But I don't really understand it. For example, it says it can
> drive the value b out but I can't see bidir being assigned to at
> all, rather just being connected to a when oe is asserted.

assign bidir =3D oe ? a : 8'bZ ;

So why is this different to bidir "being assigned to"?  It
says drive bidir with whatever value is on "a" when oe is
high.  "a" itself is assigned in the synchronous always
block:

always @ (posedge clk)
begin
    a <=3D inp;
end

This presumably shows a registered output.  If you wanted
a combinatorial I/O you'd just assign inp directly to bidir
like:

assign bidir =3D oe ? inp : 8'bZ ;

HTH,
Gabor