The world's first 3D FPGA has arrived! We have a
very compelling and
cost effective solution.

Come check it out folks. www.tierlogic.com

Jeff

Jeff,

Except you require registration to even see what it is that you have.

What are you afraid of?  Competition?

So, until you decide to stop "qualifying customers" I am afraid you
will remain a relatively unknown company.

That is OK:  the longer it takes for you to make money, the more
likely the investors pull the plug, and you go away like all the other
FPGA companies have in the past.

Good luck,

Austin

On Mar 10, 7:42=A0pm, austin
<aus...@xilinx.com> wrote:
> Jeff,
>
> Except you require registration to even see what it is that you have.
>
> What are you afraid of? =A0Competition?
>
> So, until you decide to stop "qualifying customers" I am afraid you
> will remain a relatively unknown company.
>
> That is OK: =A0the longer it takes for you to make money, the more
> likely the investors pull the plug, and you go away like all the other
> FPGA companies have in the past.
>
> Good luck,
>
> Austin

100% agree!!

not seen so dumb stupid website launch for a long time

Antti

On Mar 10, 11:46=A0am, Tier Logic
<jeff.ka...@gmail.com> wrote:
> The world's first 3D FPGA has arrived! We have a very compelling and
> cost effective solution.
>
> Come check it out folks.www.tierlogic.com
>
> Jeff

Sad.

I have a passing interest in anything proclaiming itself "new" and
"revolutionary" but I won't bother to register to get more
information.

I *might* have the next $1M+ design but it will go to standard FPGAs
because I can't find out about the promising technology on a casual
basis.
___

"Are you interested in dating me?"  "Not without a ring."  Huh?

On Mar 10, 1:11=A0pm, John_H
<newsgr...@johnhandwork.com> wrote:
> On Mar 10, 11:46=A0am, Tier Logic <jeff.ka...@gmail.com> wrote:
>
> > The world's first 3D FPGA has arrived! We have a very compelling and
> > cost effective solution.
>
> > Come check it out folks.www.tierlogic.com
>
> > Jeff
>
> Sad.
>
> I have a passing interest in anything proclaiming itself "new" and
> "revolutionary" but I won't bother to register to get more
> information.
>
> I *might* have the next $1M+ design but it will go to standard FPGAs
> because I can't find out about the promising technology on a casual
> basis.
> ___
>
> "Are you interested in dating me?" =A0"Not without a ring."
=A0Huh?

I didn't realize the *entire* site is off limits until you have
registered.  Registration means giving them your email address and
waiting for them to get back to you...  I guess they want to exclude
the little guys and I am a little guy.  So in effect, I don't exist.
To me, they don't exist.

Rick

On 3/10/2010 4:46 PM, Tier Logic wrote:
> The world's first 3D FPGA has arrived! We have a very compelling and
> cost effective solution.
>
> Come check it out folks. www.tierlogic.com
>
> Jeff

Hi Jeff,
I've examined all the old FPGAs I've found in my office, and they all 
seem to have three dimensions already. Even the old ones from 1986. This 
seems to be the biggest marketing fraud since the film 'The NeverEnding 
Story'.
Syms.

p.s. Apologies to Lionel Hutz.

Wow, tough crowd.

http://www.eetimes.com/showArticle.jhtml?articleID=223400002&cid=NL_eet

has some info for the link-inclined.  FPGA architecture looks pretty 
standard.  Value-added is almost entirely in their Tier-FPGA to 
Tier-ASIC transition, from what I can tell.  Seems to me that that 
limits their potential customers-- for really large volume pipelined 
life-cycle products, ASIC probably makes sense off the bat.  For 
low-volume, more specialty products, you're stuck at FPGA timing, so why 
not use an FPGA?  So you're left with moderate volume customers where 
time-to-market drives everything.

I'm not a business head, but I guess if you really got into a groove 
with these guys to reduce the FPGA-to-ASIC transition to a couple of 
weeks, that could be really cool for some folks.

--Josh


On 3/10/2010 2:25 PM, Symon wrote:
> On 3/10/2010 4:46 PM, Tier Logic wrote:
>> The world's first 3D FPGA has arrived! We have a very compelling and
>> cost effective solution.
>>
>> Come check it out folks. www.tierlogic.com
>>
>> Jeff
>
> Hi Jeff,
> I've examined all the old FPGAs I've found in my office, and they all
> seem to have three dimensions already. Even the old ones from 1986. This
> seems to be the biggest marketing fraud since the film 'The NeverEnding
> Story'.
> Syms.
>
> p.s. Apologies to Lionel Hutz.

On Mar 11, 8:25=A0am, Symon
<symon_bre...@hotmail.com> wrote:
>
> Hi Jeff,
> I've examined all the old FPGAs I've found in my office, and they all
> seem to have three dimensions already. Even the old ones from 1986.

Hehe ;) - yes, even Tabula are trying to spin 3D too...

 Still, getting back to the site itself, it seems they
have a Stacked-die prototype path, and the main thrust is really mask-
asic.

 The stacked die 'emulation devices' will come at a large price
premium, and their config density will need to be low (given this is
top-layer stuff).
I'd expect a power premium too...

 The advantage is you CAN get closer to real field emulation, (as
opposed to devices like Atmel's CAPxx, which can only offer bench-
emulation, via a large FPGA)

[" Free NRE
Qualifying production orders of $50k+ for converting an existing
production FPGA to a compatible TierASIC=99 device are eligible for free
NRE and conversion."]

That leaves the final chestnuts, of packaging and Price.

 One opening I can see in CPLD/FPGA space, is smaller devices with
MORE RAM. - ie really a RAM+CPLD, or
a smart ram, if you like.
 That type of product also tends to be somewhat more
stable in code, so could suit TierLogic flows.

 Full DualPort memories are very expensive, and large,
and FPGAs have low SRAM levels, until you get very large.

 The ProgLogic+Micro space is filling up: Atmel & ST target the
ramping-volume with their MASK variants, and
we have Cypress and Actel with FlashuC+ProgLogic offerings.

-jg

On Mar 11, 5:46=A0am, Tier Logic
<jeff.ka...@gmail.com> wrote:
> The world's first 3D FPGA has arrived! We have a very compelling and
> cost effective solution.
>
> Come check it out folks.www.tierlogic.com

Pity, rather a bad fumble at first hurdle.

The Prog Logic space is VERY broad indeed, and yet there is NO
indication of which parts of that TierLogic target: Even the simplest
things, like packages and speeds.

Imagine Toyota saying "We have a new product, with 4 wheels - sign up
to learn more".  ?!

-jg

On Mar 10, 3:14=A0pm, -jg
<jim.granvi...@gmail.com> wrote:
> On Mar 11, 8:25=A0am, Symon <symon_bre...@hotmail.com> wrote:
>
> > Hi Jeff,
> > I've examined all the old FPGAs I've found in my office, and they all
> > seem to have three dimensions already. Even the old ones from 1986.
>
> Hehe ;) - yes, even Tabula are trying to spin 3D too...
>
> =A0Still, getting back to the site itself, it seems they
> have a Stacked-die prototype path, and the main thrust is really mask-
> asic.
>
> =A0The stacked die 'emulation devices' will come at a large price
> premium, and their config density will need to be low (given this is
> top-layer stuff).
> I'd expect a power premium too...

Stacked die?  I read the eetimes article and didn't get anything about
stacked die from Tier Logic.  Did I read something wrong?  I thought
they were layering TFT on top of the base die to provide the config
memory which takes it out of the base die saving real estate.  I am
sure the savings is somewhat mitigated by the need for vias to the
lower layers, but still a 35% (or something like that) savings in size
is nothing to sneeze it.  I bet AMD wishes they could get that on
their CPU die right now!


> =A0The advantage is you CAN get closer to real field emulation, (as
> opposed to devices like Atmel's CAPxx, which can only offer bench-
> emulation, via a large FPGA)

They seem to be pushing their ability to more easily move to ASIC
production, but they seem to offer something to the FPGA only user as
well.  I'd be willing to bet there is a premium compared to ASICs so
they are taking a middle ground in that regard.


> [" Free NRE
> Qualifying production orders of $50k+ for converting an existing
> production FPGA to a compatible TierASIC=99 device are eligible for free
> NRE and conversion."]
>
> That leaves the final chestnuts, of packaging and Price.
>
> =A0One opening I can see in CPLD/FPGA space, is smaller devices with
> MORE RAM. - ie really a RAM+CPLD, or
> a smart ram, if you like.
> =A0That type of product also tends to be somewhat more
> stable in code, so could suit TierLogic flows.
>
> =A0Full DualPort memories are very expensive, and large,
> and FPGAs have low SRAM levels, until you get very large.
>
> =A0The ProgLogic+Micro space is filling up: Atmel & ST target the
> ramping-volume with their MASK variants, and
> we have Cypress and Actel with FlashuC+ProgLogic offerings.

I'm not clear on what you are saying about this in regards to Tier
Logic.

Rick