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Comp.Arch.FPGA | Compiling a design in Quartus that doesn't fit

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

Compiling a design in Quartus that doesn't fit - General Schvantzkoph - 2010-03-11 10:05:00

I want to be able to generate an encrypted
netlist of a core using 
Quartus. Does Quartus have a switch that allows you to compile a design 
that doesn't fit into an FPGA? The issue is that the ports on the core 
exceed the number of pins on any device.



Re: Compiling a design in Quartus that doesn't fit - Nial Stewart - 2010-03-11 10:25:00

"General Schvantzkoph"
<s...@yahoo.com> wrote in message 
news:7...@mid.individual.net...
>I want to be able to generate an encrypted netlist of a core using
> Quartus. Does Quartus have a switch that allows you to compile a design
> that doesn't fit into an FPGA? The issue is that the ports on the core
> exceed the number of pins on any device.


There are settings to allow you to compile lower level entites for incremental
compilation, although I can't remember what they are.

A quick search shows that 'virtual pin' might be what you're looking for, or lead
in the right direction.


Nial.
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Re: Compiling a design in Quartus that doesn't fit - General Schvantzkoph - 2010-03-11 11:23:00

On Thu, 11 Mar 2010 15:25:58 +0000, Nial Stewart
wrote:

> "General Schvantzkoph" <s...@yahoo.com> wrote in message
> news:7...@mid.individual.net...
>>I want to be able to generate an encrypted netlist of a core using
>> Quartus. Does Quartus have a switch that allows you to compile a design
>> that doesn't fit into an FPGA? The issue is that the ports on the core
>> exceed the number of pins on any device.
> 
> 
> There are settings to allow you to compile lower level entites for
> incremental compilation, although I can't remember what they are.
> 
> A quick search shows that 'virtual pin' might be what you're looking
> for, or lead in the right direction.
> 
> 
> Nial.

Thanks, that sounds like what I want.
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