Is it possible to get a detailed report out of
XST, listing the gates it 
has optimized out of a design? XST is removing some gates that I 
specifically put into a design, and I want to prevent this. I can use 
the XST constraints file, but I'd like to see exactly what it is doing.

Googling hasn't turned up much, yet.

Thanks
-- 
Jason Thibodeau

On Mar 26, 6:06=A0am, Jason Thibodeau
<jason.p.thibod...@gmail.com>
wrote:
> Is it possible to get a detailed report out of XST, listing the gates it
> has optimized out of a design? XST is removing some gates that I
> specifically put into a design, and I want to prevent this. I can use
> the XST constraints file, but I'd like to see exactly what it is doing.
>
> Googling hasn't turned up much, yet.
>
> Thanks
> --
> Jason Thibodeau

Not that I'm experienced but whenever I've seen a similar question
(missing logic) it's been optomised out because you haven't connected
the output to anything.  Try connecting it to a pin out (even if
that's not where you want it eventually) and see if it turns up.

Dave

On 03/25/2010 11:24 PM, David Wiltshire wrote:
> On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...@gmail.com>
> wrote:
>> Is it possible to get a detailed report out of XST, listing the gates it
>> has optimized out of a design? XST is removing some gates that I
>> specifically put into a design, and I want to prevent this. I can use
>> the XST constraints file, but I'd like to see exactly what it is doing.
>>
>> Googling hasn't turned up much, yet.
>>
>> Thanks
>> --
>> Jason Thibodeau
>
> Not that I'm experienced but whenever I've seen a similar question
> (missing logic) it's been optomised out because you haven't connected
> the output to anything.  Try connecting it to a pin out (even if
> that's not where you want it eventually) and see if it turns up.
>
> Dave

Yes, I ran across that and I connected the output. Only the last gate in 
the design is being synthesized. All the other gates, which connect to 
it, are being optimized out.

-- 
Jason Thibodeau

On 03/26/2010 12:00 PM, Jason Thibodeau wrote:
> On 03/25/2010 11:24 PM, David Wiltshire wrote:
>> On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...@gmail.com>
>> wrote:
>>> Is it possible to get a detailed report out of XST, listing the gates it
>>> has optimized out of a design? XST is removing some gates that I
>>> specifically put into a design, and I want to prevent this. I can use
>>> the XST constraints file, but I'd like to see exactly what it is doing.
>>>
>>> Googling hasn't turned up much, yet.
>>>
>>> Thanks
>>> --
>>> Jason Thibodeau
>>
>> Not that I'm experienced but whenever I've seen a similar question
>> (missing logic) it's been optomised out because you haven't connected
>> the output to anything. Try connecting it to a pin out (even if
>> that's not where you want it eventually) and see if it turns up.
>>
>> Dave
>
> Yes, I ran across that and I connected the output. Only the last gate in
> the design is being synthesized. All the other gates, which connect to
> it, are being optimized out.
>

I'd like to bump this. Any word on how Ic an stop it from optimizing my 
required logic away? Why wouldn't Xilinx just allow me to turn off 
optimization?

-- 
Jason Thibodeau

Jason Thibodeau wrote:
> I'd like to bump this. Any word on how Ic an stop it from optimizing my 
> required logic away? Why wouldn't Xilinx just allow me to turn off 
> optimization?

If you use VHDL, there are some "pragma" or "attribute"s
("set_dont_touch" or "keep" ?) that specify that a net must be kept.
It worked for me on Actel/Synplify but I don't remember the syntax.
I suppose that the same exists in Verilog.

A quick googling told me (unchecked) :
http://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0059_8.html
www.altera.com/literature/hb/qts/qts_qii51008.pdf
and more, but I couldn't spend much time on this.

HTH
yg
-- 
http://ygdes.com / http://yasep.org

Jason Thibodeau wrote:
> I'd like to bump this. Any word on how Ic an stop it from optimizing my 
> required logic away? Why wouldn't Xilinx just allow me to turn off 
> optimization?
ok in fact I have found the following :
http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir.htm
http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_keep.htm
http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm
http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_preserve.htm
just use these keywords to search in XST's docs.
_o/
yg
-- 
http://ygdes.com / http://yasep.org

On 28/03/10 21:24, whygee wrote:
> Jason Thibodeau wrote:
>> I'd like to bump this. Any word on how Ic an stop it from optimizing my 
>> required logic away? Why wouldn't Xilinx just allow me to turn off 
>> optimization?
> ok in fact I have found the following :
> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir.htm
> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_keep.htm
> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm
> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_preserve.htm
> just use these keywords to search in XST's docs.
> _o/
> yg

Hi Yg - I agree with your proposed solution - however I suggest Jason
looks on the Xilinx website for the correct XST incantations :-;

regards
Alan

-- 
Alan Fitch

On 29 Mar, 00:43, Alan Fitch
<a...@invalid.invalid> wrote:
> On 28/03/10 21:24, whygee wrote:
>
> > Jason Thibodeau wrote:
> >> I'd like to bump this. Any word on how Ic an stop it from optimizing my
> >> required logic away? Why wouldn't Xilinx just allow me to turn off
> >> optimization?
> > ok in fact I have found the following :
> >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
> >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
> >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
> >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
> > just use these keywords to search in XST's docs.
> > _o/
> > yg
>
> Hi Yg - I agree with your proposed solution - however I suggest Jason
> looks on the Xilinx website for the correct XST incantations :-;
>
> regards
> Alan
>
> --
> Alan Fitch
This should help:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
keep constraint
regards Modimo

On 03/28/2010 07:24 PM, modimo wrote:
> On 29 Mar, 00:43, Alan Fitch<a...@invalid.invalid>  wrote:
>> On 28/03/10 21:24, whygee wrote:
>>
>>> Jason Thibodeau wrote:
>>>> I'd like to bump this. Any word on how Ic an stop it from optimizing my
>>>> required logic away? Why wouldn't Xilinx just allow me to turn off
>>>> optimization?
>>> ok in fact I have found the following :
>>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
>>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
>>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
>>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d...
>>> just use these keywords to search in XST's docs.
>>> _o/
>>> yg
>>
>> Hi Yg - I agree with your proposed solution - however I suggest Jason
>> looks on the Xilinx website for the correct XST incantations :-;
>>
>> regards
>> Alan
>>
>> --
>> Alan Fitc
> This should help:
> http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
> keep constraint
> regards Modimo


I should have mentioned that I have tried all the iterations of keep 
that I could think of, the gates are still being optimized out. I tried 
both placing the keep attribute in the code, and using the xcf file, 
neither have worked. I think part of the problem is I don't know hte 
exact name of the nets being optimized out, since XST doesn't tell me 
this information in the reports.

I'm at a different machine right now, but I'll post up some code 
snippets in the morning.

Thanks for the help, all.

-- 
Jason Thibodeau

On Sun, 28 Mar 2010 21:29:31 -0400
Jason Thibodeau <j...@gmail.com> wrote:

(...)
> 
> I should have mentioned that I have tried all the iterations of keep 
> that I could think of, the gates are still being optimized out. I tried 
> both placing the keep attribute in the code, and using the xcf file, 
> neither have worked. I think part of the problem is I don't know hte 
> exact name of the nets being optimized out, since XST doesn't tell me 
> this information in the reports.


Altough it is not universal, I use the "S" (save net flag) attribute for keeping
signals from being optimized (typically for displaying them in Chipscope).

The "S" attribute is described in the Constraint Guide (cgd.pdf).


-- 
Matthieu Michon <p...@gmail.com>