On Mar 29, 4:37=A0am, Matthieu Michon
<prenom....@gmail.com> wrote:
> On Sun, 28 Mar 2010 21:29:31 -0400
>
> Jason Thibodeau <jason.p.thibod...@gmail.com> wrote:
>
> (...)
>
>
>
> > I should have mentioned that I have tried all the iterations of keep
> > that I could think of, the gates are still being optimized out. I tried
> > both placing the keep attribute in the code, and using the xcf file,
> > neither have worked. I think part of the problem is I don't know hte
> > exact name of the nets being optimized out, since XST doesn't tell me
> > this information in the reports.
>
> Altough it is not universal, I use the "S" (save net flag) attribute for =
keeping signals from being optimized (typically for displaying them in Chip=
scope).
>
> The "S" attribute is described in the Constraint Guide (cgd.pdf).
>
> --
> Matthieu Michon <prenom....@gmail.com>

I'm having problems with my main machine, so I'm posting this from
google groups, I'm the OP.

I have some gates defined in a verilog file like this:

AND2X1 Gate1 (.A(net1) , .B(net2), .Y(net3));
INVX1 gate2 (.A(net3) , .B(net4));

etc..

The entities, AND2X1 and INVX1 are defined in a library, so they
synthesize just fine.

The final gate I have:
OR2X1 gate15 (.A(bla bla), .B(...), .Y(...));

This gate, gate15 shows up in manual place and route, but the others
connected to it do not. Why is that?

I'll look into the 'S' flag, thanks.

On Fri, 26 Mar 2010 12:00:31 -0400
Jason Thibodeau <j...@gmail.com> wrote:

> On 03/25/2010 11:24 PM, David Wiltshire wrote:
> > On Mar 26, 6:06 am, Jason Thibodeau<jason.p.thibod...@gmail.com>
> > wrote:
> >> Is it possible to get a detailed report out of XST, listing the
> >> gates it has optimized out of a design? XST is removing some gates
> >> that I specifically put into a design, and I want to prevent this.
> >> I can use the XST constraints file, but I'd like to see exactly
> >> what it is doing.
> >>
> >> Googling hasn't turned up much, yet.
> >>
> >> Thanks
> >> --
> >> Jason Thibodeau
> >
> > Not that I'm experienced but whenever I've seen a similar question
> > (missing logic) it's been optomised out because you haven't
> > connected the output to anything.  Try connecting it to a pin out
> > (even if that's not where you want it eventually) and see if it
> > turns up.
> >
> > Dave
> 
> Yes, I ran across that and I connected the output. Only the last gate
> in the design is being synthesized. All the other gates, which
> connect to it, are being optimized out.
> 

This may be a silly question, but exactly what does the logic that's
being optimized out do?

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order