I think I have about had it with VHDL.  I've been
using the
numeric_std library and eventually learned how to get around the
issues created by strong typing although it can be very arcane at
times.  I have read about a few suggestions people are making to help
with some aspects of the language, like a selection operator like
Verilog has.  But it just seems like I am always fighting some aspect
of the VHDL language.

I guess part of my frustration is that I have yet to see where strong
typing has made a real difference in my work... at least an
improvement.  My customer uses Verilog and has mentioned several times
how he had tried using VHDL and found it too arcane to bother with.
He works on a much more practical level than I often do and it seems
to work well for him.

One of my goals over the summer is to teach myself Verilog so that I
can use it as well as I currently use VHDL.  Then I can make a fully
informed decision about which I will continue to use.  I'd appreciate
pointers on good references, web or printed.

Without starting a major argument, anyone care to share their feelings
on the differences in the two languages?

Rick

Before the fixed and floating point packages came
out, I would have
said there is little difference regarding RTL capabilities between
Verilog and VHDL. But those two packages revealed a fundamental
strength of VHDL that simply does not exist in verilog. By simply
writing a new package, a whole new capability was created that would
take a substantial language change in Verilog. Yes, the as-released
packages took advantage of features only available in a related change
in the language itself, but the "compatibility" packages ably
demonstrate that the working concept is viable even within the
confines the original language, thus demonstrating the true strengh of
the basic language of VHDL.

Not that the fixed/floating point packages are nirvana, but they do
represent a huge step in the right direction. If we only had
assignment operator overloading in VHDL, it would be much closer...
Still, that's a capability much closer to reality in VHDL than in
Verilog. Sure, verilog has many "built-in" tricks, but they are only
applicable to the existing type structure, and cannot be expanded upon
without revising the language itself.

Even before the fixed/floating point packages, integers simply work in
VHDL (within the range limitations), whereas in Verilog, they don't
always, but they also don't complain when they don't work either.

In general, strong typing and built-in bounds checking in VHDL catch
more problems, closer to the source of the problems, with no
additional code being written, than is possible in Verilog without
having to write A LOT of extra code. It seems for almost every weak-
typing-enabled shortcut in verilog, there is also a hidden, often
silent, "gotcha" to go along with it.

Andy

On Apr 9, 9:07=A0am, rickman
<gnu...@gmail.com> wrote:
> I think I have about had it with VHDL. =A0I've been using the
> numeric_std library and eventually learned how to get around the
> issues created by strong typing although it can be very arcane at
> times. =A0I have read about a few suggestions people are making to help
> with some aspects of the language, like a selection operator like
> Verilog has. =A0But it just seems like I am always fighting some aspect
> of the VHDL language.
>
> I guess part of my frustration is that I have yet to see where strong
> typing has made a real difference in my work... at least an
> improvement. =A0My customer uses Verilog and has mentioned several times
> how he had tried using VHDL and found it too arcane to bother with.
> He works on a much more practical level than I often do and it seems
> to work well for him.
>
> One of my goals over the summer is to teach myself Verilog so that I
> can use it as well as I currently use VHDL. =A0Then I can make a fully
> informed decision about which I will continue to use. =A0I'd appreciate
> pointers on good references, web or printed.
>
> Without starting a major argument, anyone care to share their feelings
> on the differences in the two languages?
>
> Rick

The best online references are the Sutherland Verilog references.
There is an online HTML reference for Verilog 95 (excellent), and a
PDF for Verilog 2001 (good):

http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html
http://sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.p=
df

Cliff Cummings has a lot of good papers on Verilog at his site:

http://sunburst-design.com/papers/

In particular, if you read and carefully grok his paper about non-
blocking vs. blocking assignments, you will be well on your way to
being a Verilog wizard:

http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

Regards,
Pat

On Apr 9, 10:07=A0am, rickman
<gnu...@gmail.com> wrote:
> I think I have about had it with VHDL. =A0I've been using the
> numeric_std library and eventually learned how to get around the
> issues created by strong typing although it can be very arcane at
> times. =A0I have read about a few suggestions people are making to help
> with some aspects of the language, like a selection operator like
> Verilog has. =A0But it just seems like I am always fighting some aspect
> of the VHDL language.
>
> I guess part of my frustration is that I have yet to see where strong
> typing has made a real difference in my work... at least an
> improvement. =A0My customer uses Verilog and has mentioned several times
> how he had tried using VHDL and found it too arcane to bother with.
> He works on a much more practical level than I often do and it seems
> to work well for him.
>
> One of my goals over the summer is to teach myself Verilog so that I
> can use it as well as I currently use VHDL. =A0Then I can make a fully
> informed decision about which I will continue to use. =A0I'd appreciate
> pointers on good references, web or printed.
>
> Without starting a major argument, anyone care to share their feelings
> on the differences in the two languages?
>
> Rick

At the end of the day, it really comes down to how you can be more
productive.  If you tend to code with many levels of abstraction
you may do better with VHDL.  I find that I am more productive
with Verilog, but it could be because I tend to look at hardware
at a fairly detailed level, a bottom-up approach if you will.  I
inherited Verilog projects at my current place of employment and
just stuck with the language as it grew on me.  At one point I
read Thomas & Moorby's green book from cover to cover.  However
it described Verilog 95, not the more commonly used Verilog 2001,
and was not a particularly good reference book.  I keep a copy
of the Doulos Golden Reference handy for the bits I don't use
every day.

Good Luck,
Gabor

In comp.arch.fpga rickman
<g...@gmail.com> wrote:
(snip)
 
> Without starting a major argument, anyone care to share their feelings
> on the differences in the two languages?

I started with verilog, as that is what others I was working with
were doing, and was also told that it was a better choice for
previous C programmers.  (Not that I believe that HDL should be
related to a software language.)

At some point, I learned to read VHDL, at least enough to convert
an module to verilog when needed, or to understand why something
didn't work the way I thought it should.  (I had one project with
schematic capture, VHDL, and AHDL, and then I started adding
verilog to it.)  

It seems to me that verilog, similar to C, gets the ideas across
without being excessively wordy.  In comparison to some other
languages, I find the convenience in C of converting between
char and int without the need for any special conversion operation
(such as the Fortran CHAR function) convenient.  

Well, I write my verilog mostly using continuous assignment,
with a fairly small amount of behavioral verilog.  For those who
prefer behavioral coding, the recommendation might be different.

-- glen

On Apr 9, 3:07=A0pm, rickman
<gnu...@gmail.com> wrote:
> I think I have about had it with VHDL. =A0I've been using the
> numeric_std library and eventually learned how to get around the
> issues created by strong typing although it can be very arcane at
> times. =A0I have read about a few suggestions people are making to help
> with some aspects of the language, like a selection operator like
> Verilog has. =A0But it just seems like I am always fighting some aspect
> of the VHDL language.
>
> I guess part of my frustration is that I have yet to see where strong
> typing has made a real difference in my work... at least an
> improvement.

I think Andy has it about right.  If you think signed arithmetic
was a tad messy in VHDL, wait until you find how successfully you
can be screwed by Verilog.  The really cool thing is that Verilog
is polite, and doesn't tell you when it's screwing you.  At least
VHDL is up-front about it.  How many times have you created a
design in VHDL that got through compilation, but was broken in
a surprising way that was directly related to a quirk of the
language?  Betcha you can count the occurrences on one hand.
Verilog does that to you all the time; it has startlingly
weak compile-time checking, and only slightly stronger
elaboration-time checking.

How comfortable are you with most-significant bits being
silently lost when you copy a wide vector into a narrow
one?  How about signed values being silently zero-filled
to the width of a wider target?

>=A0My customer uses Verilog and has mentioned several times
> how he had tried using VHDL and found it too arcane to bother with.
> He works on a much more practical level than I often do and it seems
> to work well for him.

Is "practical" here a euphemism?

> One of my goals over the summer is to teach myself Verilog so that I
> can use it as well as I currently use VHDL. =A0Then I can make a fully
> informed decision about which I will continue to use. =A0I'd appreciate
> pointers on good references, web or printed.

Good luck.  As I've pointed out on many occasions, the textbook
situation is much less satisfactory for Verilog than it is
for VHDL.  Whatever you do, PLEASE get yourself a copy of
Sutherland's Verilog Gotchas book (much of it is available free
online).  You may not understand all of it at first, but
you sure will want to revisit it later.  It's just a pity
that it's incomplete and doesn't cover ALL the many ways
in which Verilog can silently mess you up.

To be serious for a moment: a training class from a
reputable independent provider will save you a ton
of money in the long run.  Your time is valuable.

> Without starting a major argument, anyone care to share their feelings
> on the differences in the two languages?

Errrrm, I think I just did.
--
Jonathan Bromley

rickman <g...@gmail.com> wrote:

>I think I have about had it with VHDL.  I've been using the
>numeric_std library and eventually learned how to get around the
>issues created by strong typing although it can be very arcane at
>times.  I have read about a few suggestions people are making to help
>with some aspects of the language, like a selection operator like
>Verilog has.  But it just seems like I am always fighting some aspect
>of the VHDL language.
>
>I guess part of my frustration is that I have yet to see where strong
>typing has made a real difference in my work... at least an

I also write a lot of C. Over the past years I've noticed that C
compilers (GCC to be exact) have become much more strict when it comes
to type checking. No more automatic casting. I'm sure this is done for
a good reason!

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On Apr 9, 2:07=A0pm, Jonathan Bromley
<s...@oxfordbromley.plus.com>
wrote:

> > I guess part of my frustration is that I have yet to see where strong
> > typing has made a real difference in my work... at least an
> > improvement.
>
> I think Andy has it about right. =A0If you think signed arithmetic
> was a tad messy in VHDL, wait until you find how successfully you
> can be screwed by Verilog. =A0The really cool thing is that Verilog
> is polite, and doesn't tell you when it's screwing you. =A0At least
> VHDL is up-front about it. =A0How many times have you created a
> design in VHDL that got through compilation, but was broken in
> a surprising way that was directly related to a quirk of the
> language? =A0Betcha you can count the occurrences on one hand.
> Verilog does that to you all the time; it has startlingly
> weak compile-time checking, and only slightly stronger
> elaboration-time checking.
>
> How comfortable are you with most-significant bits being
> silently lost when you copy a wide vector into a narrow
> one? =A0How about signed values being silently zero-filled
> to the width of a wider target?

Personally?  Very.

As the proponents of agile programming languages (I love Python) will
point out, the sort of typing errors that you are describing are but a
small subset of the ways you can screw up your design.  Any reasonable
testbench will find these issues.

And BTW, (IMO) it's *much* easier to code a reasonable testbench in
verilog than in VHDL.  But, obviously, your mileage varies.

Regards,
Pat

On Apr 9, 2:31=A0pm, n...@puntnl.niks (Nico
Coesel) wrote:

> I also write a lot of C. Over the past years I've noticed that C
> compilers (GCC to be exact) have become much more strict when it comes
> to type checking. No more automatic casting. I'm sure this is done for
> a good reason!

I used to write a lot of Modula-2.  It was much better than (pre-ANSI)
C (and in fact was one of the contenders for the language the DOD uses
as ADA now, which is what VHDL was based on).  IMO, Modula-2 was at a
sweet spot on verbosity vs. checking.  But then ANSI C came along, and
was "good enough".  Combine that with the compilers getting smart
enough to let you know about potential pitfalls, and there wasn't much
room for another language in the ecological niche that C fills, and,
for example, the Modula-2 ecosystem dwindled to nothing, and the Ada
ecosystem limped along, primarily propped up by the DOD and
educational institutions.

I think there really is a good corollary with HDLs there -- Verilog
synthesizers and simulators have a lot of options for telling you
about warnings and things, and Verilog occupies the same sort of sweet
spot as C, with only a few people preferring Ada or VHDL over C or
Verilog.

Regards,
Pat

On Apr 10, 2:07=A0am, rickman
<gnu...@gmail.com> wrote:
> One of my goals over the summer is to teach myself Verilog so that I
> can use it as well as I currently use VHDL. =A0Then I can make a fully
> informed decision about which I will continue to use. =A0I'd appreciate
> pointers on good references, web or printed.

You could also look at Jan Decaluwe's MyHDL ?

http://www.myhdl.org/doku.php

and a case example here :

http://www.jandecaluwe.com/hdldesign/digmac.html

this allows you to go in either direction, to VHDL to Verilog, and to
'test early'.

-jg