On May 12, 7:59=A0am, KJ
<kkjenni...@sbcglobal.net> wrote:
> >> On Apr 9, 10:07 am, rickman <gnu...@gmail.com> wrote:
> > > > I guess part of my frustration is that I have yet to see where stro=
ng
> > > > typing has made a real difference in my work... at least an
> > > > improvement.
> > On May 12, 12:20 am, rickman <gnu...@gmail.com> wrote:
> > I know
> > of a few instances of when strong typing found bugs for me before they
> > turned into lab bug searches... which is one of the main reasons for
> > using such features. =A0The earlier in the process bugs are found, the
> > easier they are found and the smaller the impact. =A0
>
> It seems you've already (re)discovered actual examples where type
> checking can be useful
>
> > Still, there is a
> > cost and the question is whether the cost is justified...
>
> Depends strongly on the cost of a bug.

Yep!  Today we found the hardest bug to date on this project.  It was
a configuration error... software setting up the hardware.  No amount
of type checking would have helped to find that one.  That is my
point.  VHDL may help prevent some bugs, but there is a lot more to
minimizing bugs than what can be forced on you by tools.  Effective
design is a holistic practice that has to take into account the unique
aspects of each design optimizing the process to match the risk
areas.  I actually knew that the interface of my board to the rest of
the system was the high risk part of the design, both in terms of the
system itself and in terms of communicating the details.  I failed to
give this risk factor enough attention.  I tried taking a shortcut of
putting too much effort into the test bench and not doing bench
testing (not the same as test bench testing) before turning the design
over to the customer for integration.

It should be smooth sailing from here on.  So at least I'll have more
time to post here and later look into the advantages of Verilog.

Rick