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Comp.Arch.FPGA | I hit the wall

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I hit the wall - jmariano - 2010-05-09 16:49:00

Dear all

Here's my problem: I've developed an VHDL IP in ISE and integrate it
into a Microblaze peripheral using the  "create and import peripheral"
tool. My IP uses 3 read only and one write only registers to interface
with the IPIC module. The IP has one ENB input that must be set to
start the operation of the FSM within, and once the IP is running, it
sets the RUN output. I have connected the ENB signal to one register
(the control register) and the RUN signal to another register (the
status register). (I know, this is not very elegant, but I'm just
trying to make the thing work)

Now, the strange thing is this: when I do functional simulation in
modelsim, the IP works as expected. When I do BFM Simulation in
Platform Studio, the module also works, at least as far as I can tell.
The problem is that when I integrate the module into my system and set
the control register from the C code, the IP does not work, ie, the
status register is not set. My first thought was that I made a mistake
at the IPIC register interface, so I use a test version of my IP with
RUN <= ENB and when I set ENB, the RUN is set inside the IP. So the
problem must be on the IP.

I have checked and double checked the code and I couldn't find noting
obviously wrong, but since I don't have much experience in VHDL, I
must be missing something or doing some stupid error.

Does any one have some ideas? I really appreciate a fresh look at my
code.

Regards,

jmariano

(ISE 7.1i, XPS 7.1i, Spartan-3 Starter Kit Board)