Hello,

I had a look into the V6 Datasheets, but couldn't find a direct clue.
Would it be possible to implemement two PCIe Endpoints in one Virtex-6
FPGA? Most of the V6-Devices offer two hard PCIe blocks and the PCIe
root device should initiate link training on all lanes. If I understand
this correctly, it should be possible, to build a card with for example
a x8 finger, 4 lanes to one PCIe hard block, 4 to the other, which would
identify to the host system as two independent x4 systems but plugged
into one x8 slot. Am I missing something?
Comments are greatly appreciated.

Cheers,
HE

I would of thought if the PCIe spec says that you
can do this then it wouldbe possible to do it. If the Virtex 6 hardblocks operate independently fromeach other then it comes down to what the PCIe spec says.

Regards

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On May 11, 6:55=A0am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I would of thought if the PCIe spec says that you can do this then it wou=
ld
> be possible to do it. If the Virtex 6 hardblocks operate independently fr=
om
> each other then it comes down to what the PCIe spec says.
>
> Regards
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

I don't think the PCIe specification requires a system to
connect to multiple endpoints in a multi-lane slot.  In fact
I would bet that if you tried this in a typical PC you would
at best get a single 4-lane endpoint detected and at worst
a "broken" 8-lane endpoint, due to the hardware connections
to the second 4 lanes.  It's also possible that some systems
would allow this sort of connection, but if you look at
typical PCIe switches, it would mean they would need to
allocate more switch resources to the slot to handle what
is probably an unusual case.  In my experience with PC
motherboards, economics are always the deciding factor
in what gets supported.  Corner cases are often thrown
out the window when they incur any extra cost.

On 11 Mai, 17:21, Gabor <ga...@alacron.com>
wrote:
> On May 11, 6:55=A0am, "maxascent"
>
> <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> > I would of thought if the PCIe spec says that you can do this then it w=
ould
> > be possible to do it. If the Virtex 6 hardblocks operate independently =
from
> > each other then it comes down to what the PCIe spec says.
>
> > Regards
>
> > Jon =A0 =A0 =A0 =A0
>
> > --------------------------------------- =A0 =A0 =A0 =A0
> > Posted throughhttp://www.FPGARelated.com
>
> I don't think the PCIe specification requires a system to
> connect to multiple endpoints in a multi-lane slot. =A0In fact
> I would bet that if you tried this in a typical PC you would
> at best get a single 4-lane endpoint detected
You probably would get a single 1-lane endpoint.
Many mainboards will sync a 8x slot only at 8x and 1x width.
This is sufficient to meet the spec.

For the switch chips that I know the information, which lanes
belong to one port is hardwire by strap pins, so there can only be
one port per slot.

Kolja