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Comp.Arch.FPGA | what is the fmax of the simple dual port ram in the altera fpga
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what is the fmax of the simple dual port ram in the altera fpga - smart0604 - 2010-05-11 14:57:00
I used the simple dual port ram in quartus with the altera fpga,but when isimulate it in 100Mhz, the read data isn't what i haved writen in. but theclassic timing analyzer shows the fmax is about 200Mhz.could anybody helpme. I am so bothered with it. --------------------------------------- Posted through http://www.FPGARelated.com
Re: what is the fmax of the simple dual port ram in the altera fpga - Nial Stewart - 2010-05-12 04:18:00
"smart0604" <smart0604@n_o_s_p_a_m.163.com> wrote in message news:v...@giganews.com... >I used the simple dual port ram in quartus with the altera fpga,but when i > simulate it in 100Mhz, the read data isn't what i haved writen in. but the > classic timing analyzer shows the fmax is about 200Mhz.could anybody help > me. I am so bothered with it. Are you using fully synchronous design? Have you simulated the design to see what's happening? The first is essential, the second is highly recommended! Nial.______________________________
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Re: what is the fmax of the simple dual port ram in the altera fpga - John_H - 2010-05-12 06:34:00
On May 11, 2:57=A0pm, "smart0604" <smart0604@n_o_s_p_a_m.163.com> wrote: > I used the simple dual port ram in quartus with the altera fpga,but when = i > simulate it in 100Mhz, the read data isn't what i haved writen in. but th= e > classic timing analyzer shows the fmax is about 200Mhz.could anybody help > me. I am so bothered with it. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Do you expect the read data to show up the moment the read address is valid? Or perhaps after the clock transition which samples the valid read address?______________________________
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