If anyone out there uses Xilinx ISE Design Suite
11, I need your help!!

According to this information 
[link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link]
ISE 11 should be running verilog 2001, however when I try to run thearithmetic shift ">>>" it does not populate 1's for negative numbers as
itshould.

Does anyone have any advice on how to correct this problem?	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Jun 3, 1:48=A0pm, "shannon"
<sesilver@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> If anyone out there uses Xilinx ISE Design Suite 11, I need your help!!
>
> According to this information
> [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link]
> ISE 11 should be running verilog 2001, however when I try to run the
> arithmetic shift ">>>" it does not populate 1's for negative
numbers as i=
t
> should.
>
> Does anyone have any advice on how to correct this problem? =A0 =A0 =A0 =
=A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

There was a thread on this topic in comp.lang.verilog

You can always work around the problem using >> like:
 reg [15:0] signed_vector;

. . .
  some_vector <=3D {16{signed_vector[15]},signed_vector} >> shift_val;
 (where shift_val is less than or equal to 16)
. . .

to copy the MSB as you shift right.  Did you check if
this was fixed in 12.1?

Regards,
Gabor