Hi Guys,

I am just wondering if there are any standard ways of disabling an ip
core after an evaluation period of say 30 days. I am trying to provide
a potential customer a ip core  but don't want them to continue using
it after the eval license period expires. The core will run on Xilinx
Spartan3 FPGAs.

Any suggestions will be much appreciated.

Regards
Sudhir

Sudhir Singh <S...@email.com>
wrote:
 
> I am just wondering if there are any standard ways of disabling an ip
> core after an evaluation period of say 30 days. I am trying to provide
> a potential customer a ip core  but don't want them to continue using
> it after the eval license period expires. The core will run on Xilinx
> Spartan3 FPGAs.

Considering the ability to change the date on the computer,
it is pretty hard to stop people from using something past 
a given date.   Once the bit file is generated, it is pretty
much impossible.

The only ways I can think of would require a response from you.
One possiblility is that you (on your machine) do the actual
synthesis and P&R.  

Otherwise, if the license agreement has a large penalty for
using it past 30 days, and you catch them using it...

-- glen

glen herrmannsfeldt <g...@ugcs.caltech.edu>
writes:

> Sudhir Singh <S...@email.com> wrote:
>  
>> I am just wondering if there are any standard ways of disabling an ip
>> core after an evaluation period of say 30 days. I am trying to provide
>> a potential customer a ip core  but don't want them to continue using
>> it after the eval license period expires. The core will run on Xilinx
>> Spartan3 FPGAs.
>
> Considering the ability to change the date on the computer,
> it is pretty hard to stop people from using something past 
> a given date.   Once the bit file is generated, it is pretty
> much impossible.

Well, at least the licensable Xilinx IP I've used included some kind
of timer in the bitfile itself if there's no license, so that the
block works for a few hours and then quits. 

Anssi Saari <a...@sci.fi> wrote:
 
>> Sudhir Singh <S...@email.com> wrote:
  
>>> I am just wondering if there are any standard ways of disabling an ip
>>> core after an evaluation period of say 30 days. I am trying to provide
>>> a potential customer a ip core  but don't want them to continue using
>>> it after the eval license period expires. The core will run on Xilinx
>>> Spartan3 FPGAs.

(then I wrote)

>> Considering the ability to change the date on the computer,
>> it is pretty hard to stop people from using something past 
>> a given date.   Once the bit file is generated, it is pretty
>> much impossible.
 
> Well, at least the licensable Xilinx IP I've used included some kind
> of timer in the bitfile itself if there's no license, so that the
> block works for a few hours and then quits. 

Yes, I had forgotten about the ones that count clock cycles.
But that doesn't help if you want a specific time or date.

Even so, one could probably find a way to disable the counter.
(I don't know if reset will reset the counter or not, otherwise
one can always reload the device.)

I was unsure from your original post if you meant the ability
to generate bitfiles, or the ability to use them.

If the device has internet access, you could use an NTP server
to get the date/time.  That would take a lot of logic, though!

-- glen

On Tue, 08 Jun 2010 16:53:43 -0700, Sudhir Singh
wrote:

> Hi Guys,
> 
> I am just wondering if there are any standard ways of disabling an ip
> core after an evaluation period of say 30 days. I am trying to provide a
> potential customer a ip core  but don't want them to continue using it
> after the eval license period expires. The core will run on Xilinx
> Spartan3 FPGAs.
> 
> Any suggestions will be much appreciated.
> 
> Regards
> Sudhir

Xilinx doesn't have a mechanism yet for generating an IP license, they 
plan to have one that uses a new IEEE standard but that won't happen for 
a year.

Altera does have tools that allow you to encrypt your source code and 
then generate a flexlm license that can restrict the type of FPGA it can 
go into, allow simulation only or just synthesis, and the time limits for 
the IP. However once you've generated a bit file it's good forever, there 
is no way to have a bit file that's time limited.