Hi,

I'm somewhat familiar with synthesis and Verilog but I am quite new torunning the designs on FPGAs. I have a complex design of a processor that Iam trying to get running on a Virtex 5 FPGA in a BEE3 module. The designsynthesizes and goes through translate, map and par in Xilinx ISE 10.1 butit does not seem to run correctly when programmed on the FPGA. 

ISE says that all timing constraints have been met and the static timingreport shows that it does too. What I am going to do now is look at thepost-par simulation and see if there's a problem. Is there anything thatmaybe is a common mistake that I should also look into?

I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Anysuggestions will be appreciated.

Thanks,
Brandon

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On 6/9/2010 8:01 AM, BrandonD wrote:
> Hi,
>
> I'm somewhat familiar with synthesis and Verilog but I am quite new to
> running the designs on FPGAs. I have a complex design of a processor that I
> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design
> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but
> it does not seem to run correctly when programmed on the FPGA.
>
> ISE says that all timing constraints have been met and the static timing
> report shows that it does too. What I am going to do now is look at the
> post-par simulation and see if there's a problem. Is there anything that
> maybe is a common mistake that I should also look into?
>
> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Any
> suggestions will be appreciated.
>
> Thanks,
> Brandon
>
> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Anything other than single clock synchronous logic isn't represented in 
your timing constraints; so anywhere that you're using a clock other 
than your derived 50 is worth another look.  This includes any logic 
running off of a combinationally gated clock.  You said you're used to 
synthesis but not FPGAs; if that means ASICs then one thing to be aware 
of is that clock nets are a lot more sacred in FPGAs.

Unless you've specified your external OFFSET IN/OUT constraints properly 
(this is rare), then your constraints don't properly cover your 
relationships to external hardware.  Worth another look.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

By being familiar with synthesis, I mean I'm a
student and have had somecoursework with the design and synthesis, but projects ended there. To behonest, they were more on the design aspect so I am familiar with thesynthesis process but not too experienced with it.

I do not use any gated clocks and all of my sequential logic runs of thesame edge of the same 50 MHz clock except for the reset logic when the DCMis stabilizing. 

I have not set any OFFSET IN/OUT constraints, do you know where I can getmore information about doing that?

Thanks,
Brandon

>On 6/9/2010 8:01 AM, BrandonD wrote:
>> Hi,
>>
>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>> running the designs on FPGAs. I have a complex design of a processorthat I
>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. Thedesign
>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1but
>> it does not seem to run correctly when programmed on the FPGA.
>>
>> ISE says that all timing constraints have been met and the statictiming
>> report shows that it does too. What I am going to do now is look at the
>> post-par simulation and see if there's a problem. Is there anythingthat
>> maybe is a common mistake that I should also look into?
>>
>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.Any
>> suggestions will be appreciated.
>>
>> Thanks,
>> Brandon
>>
>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>Anything other than single clock synchronous logic isn't represented in 
>your timing constraints; so anywhere that you're using a clock other 
>than your derived 50 is worth another look.  This includes any logic 
>running off of a combinationally gated clock.  You said you're used to 
>synthesis but not FPGAs; if that means ASICs then one thing to be aware 
>of is that clock nets are a lot more sacred in FPGAs.
>
>Unless you've specified your external OFFSET IN/OUT constraints properly 
>(this is rare), then your constraints don't properly cover your 
>relationships to external hardware.  Worth another look.
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

By being familiar with synthesis, I mean I'm a
student and have had somecoursework with the design and synthesis, but projects ended there. To behonest, they were more on the design aspect so I am familiar with thesynthesis process but not too experienced with it.

I do not use any gated clocks and all of my sequential logic runs of thesame edge of the same 50 MHz clock except for the reset logic when the DCMis stabilizing. 

I have not set any OFFSET IN/OUT constraints, do you know where I can getmore information about doing that?

Thanks,
Brandon

>On 6/9/2010 8:01 AM, BrandonD wrote:
>> Hi,
>>
>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>> running the designs on FPGAs. I have a complex design of a processorthat I
>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. Thedesign
>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1but
>> it does not seem to run correctly when programmed on the FPGA.
>>
>> ISE says that all timing constraints have been met and the statictiming
>> report shows that it does too. What I am going to do now is look at the
>> post-par simulation and see if there's a problem. Is there anythingthat
>> maybe is a common mistake that I should also look into?
>>
>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.Any
>> suggestions will be appreciated.
>>
>> Thanks,
>> Brandon
>>
>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>Anything other than single clock synchronous logic isn't represented in 
>your timing constraints; so anywhere that you're using a clock other 
>than your derived 50 is worth another look.  This includes any logic 
>running off of a combinationally gated clock.  You said you're used to 
>synthesis but not FPGAs; if that means ASICs then one thing to be aware 
>of is that clock nets are a lot more sacred in FPGAs.
>
>Unless you've specified your external OFFSET IN/OUT constraints properly 
>(this is rare), then your constraints don't properly cover your 
>relationships to external hardware.  Worth another look.
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Jun 9, 12:45=A0pm, "BrandonD"
<BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> By being familiar with synthesis, I mean I'm a student and have had some
> coursework with the design and synthesis, but projects ended there. To be
> honest, they were more on the design aspect so I am familiar with the
> synthesis process but not too experienced with it.
>
> I do not use any gated clocks and all of my sequential logic runs of the
> same edge of the same 50 MHz clock except for the reset logic when the DC=
M
> is stabilizing.
>
> I have not set any OFFSET IN/OUT constraints, do you know where I can get
> more information about doing that?
>
> Thanks,
> Brandon
>
>
>
>
>
> >On 6/9/2010 8:01 AM, BrandonD wrote:
> >> Hi,
>
> >> I'm somewhat familiar with synthesis and Verilog but I am quite new to
> >> running the designs on FPGAs. I have a complex design of a processor
> that I
> >> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
> design
> >> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
> but
> >> it does not seem to run correctly when programmed on the FPGA.
>
> >> ISE says that all timing constraints have been met and the static
> timing
> >> report shows that it does too. What I am going to do now is look at th=
e
> >> post-par simulation and see if there's a problem. Is there anything
> that
> >> maybe is a common mistake that I should also look into?
>
> >> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
> Any
> >> suggestions will be appreciated.
>
> >> Thanks,
> >> Brandon
>
> >> --------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0
> >> Posted throughhttp://www.FPGARelated.com
>
> >Anything other than single clock synchronous logic isn't represented in
> >your timing constraints; so anywhere that you're using a clock other
> >than your derived 50 is worth another look. =A0This includes any logic
> >running off of a combinationally gated clock. =A0You said you're used to
> >synthesis but not FPGAs; if that means ASICs then one thing to be aware
> >of is that clock nets are a lot more sacred in FPGAs.
>
> >Unless you've specified your external OFFSET IN/OUT constraints properly
> >(this is rare), then your constraints don't properly cover your
> >relationships to external hardware. =A0Worth another look.
>
> >--
> >Rob Gaddi, Highland Technology
> >Email address is currently out of order
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

You may want to look at the "blogs" section of the Xilinx
web forums.  There is a 5-part piece on timing constraints
that is quite useful when you're getting started.

Also if you have severe problems, like it looks like
nothing works at all, you could have a loop in the
reset generation logic.  Remember that the output of
a DCM does not toggle until locked, so using it to
release reset to the DCM will lock up the system
because the reset prevents the DCM from locking.

Regards,
Gabor

On 6/9/2010 9:45 AM, BrandonD wrote:
> By being familiar with synthesis, I mean I'm a student and have had some
> coursework with the design and synthesis, but projects ended there. To be
> honest, they were more on the design aspect so I am familiar with the
> synthesis process but not too experienced with it.
>
> I do not use any gated clocks and all of my sequential logic runs of the
> same edge of the same 50 MHz clock except for the reset logic when the DCM
> is stabilizing.
>
> I have not set any OFFSET IN/OUT constraints, do you know where I can get
> more information about doing that?
>
> Thanks,
> Brandon
>
>> On 6/9/2010 8:01 AM, BrandonD wrote:
>>> Hi,
>>>
>>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>>> running the designs on FPGAs. I have a complex design of a processor
> that I
>>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
> design
>>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
> but
>>> it does not seem to run correctly when programmed on the FPGA.
>>>
>>> ISE says that all timing constraints have been met and the static
> timing
>>> report shows that it does too. What I am going to do now is look at the
>>> post-par simulation and see if there's a problem. Is there anything
> that
>>> maybe is a common mistake that I should also look into?
>>>
>>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
> Any
>>> suggestions will be appreciated.
>>>
>>> Thanks,
>>> Brandon
>>>
>>> 	
>>> 					
>>> ---------------------------------------		
>>> Posted through http://www.FPGARelated.com
>>
>> Anything other than single clock synchronous logic isn't represented in
>> your timing constraints; so anywhere that you're using a clock other
>> than your derived 50 is worth another look.  This includes any logic
>> running off of a combinationally gated clock.  You said you're used to
>> synthesis but not FPGAs; if that means ASICs then one thing to be aware
>> of is that clock nets are a lot more sacred in FPGAs.
>>
>> Unless you've specified your external OFFSET IN/OUT constraints properly
>> (this is rare), then your constraints don't properly cover your
>> relationships to external hardware.  Worth another look.
>>
>> --
>> Rob Gaddi, Highland Technology
>> Email address is currently out of order
>> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

I hope this is a stupid question but....it does simulate correctly, right?

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

It does simulate behaviorally correctly. I forgot
to mention that part.

You were right about the loop of the reset signal back to the DCM. I didexactly that. I've fixed that problem and it still appears to be workingincorrectly. I am going to try post-par simulation to see how that looks. 

I will read up on the constraints as well.


>On 6/9/2010 9:45 AM, BrandonD wrote:
>> By being familiar with synthesis, I mean I'm a student and have hadsome
>> coursework with the design and synthesis, but projects ended there. Tobe
>> honest, they were more on the design aspect so I am familiar with the
>> synthesis process but not too experienced with it.
>>
>> I do not use any gated clocks and all of my sequential logic runs ofthe
>> same edge of the same 50 MHz clock except for the reset logic when theDCM
>> is stabilizing.
>>
>> I have not set any OFFSET IN/OUT constraints, do you know where I canget
>> more information about doing that?
>>
>> Thanks,
>> Brandon
>>
>>> On 6/9/2010 8:01 AM, BrandonD wrote:
>>>> Hi,
>>>>
>>>> I'm somewhat familiar with synthesis and Verilog but I am quite newto
>>>> running the designs on FPGAs. I have a complex design of a processor
>> that I
>>>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
>> design
>>>> synthesizes and goes through translate, map and par in Xilinx ISE10.1
>> but
>>>> it does not seem to run correctly when programmed on the FPGA.
>>>>
>>>> ISE says that all timing constraints have been met and the static
>> timing
>>>> report shows that it does too. What I am going to do now is look atthe
>>>> post-par simulation and see if there's a problem. Is there anything
>> that
>>>> maybe is a common mistake that I should also look into?
>>>>
>>>> I am using a DCM to turn the 100 MHz system clock into a 50 MHzclock.
>> Any
>>>> suggestions will be appreciated.
>>>>
>>>> Thanks,
>>>> Brandon
>>>>
>>>> 	
>>>> 					
>>>> ---------------------------------------		
>>>> Posted through http://www.FPGARelated.com
>>>
>>> Anything other than single clock synchronous logic isn't representedin
>>> your timing constraints; so anywhere that you're using a clock other
>>> than your derived 50 is worth another look.  This includes any logic
>>> running off of a combinationally gated clock.  You said you're used to
>>> synthesis but not FPGAs; if that means ASICs then one thing to beaware
>>> of is that clock nets are a lot more sacred in FPGAs.
>>>
>>> Unless you've specified your external OFFSET IN/OUT constraintsproperly
>>> (this is rare), then your constraints don't properly cover your
>>> relationships to external hardware.  Worth another look.
>>>
>>> --
>>> Rob Gaddi, Highland Technology
>>> Email address is currently out of order
>>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>I hope this is a stupid question but....it does simulate correctly,right?
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Wed, 9 Jun 2010 15:05:23 -0700 (PDT)
Gabor <g...@alacron.com> wrote:

(...)
> Also if you have severe problems, like it looks like
> nothing works at all, you could have a loop in the
> reset generation logic.  Remember that the output of
> a DCM does not toggle until locked, so using it to
> release reset to the DCM will lock up the system
> because the reset prevents the DCM from locking.
> 
> Regards,
> Gabor


To follow on with the DCM feature, performing an initial DCM reset with the timings in
compliance with the user-guide and datasheet is a must (with special care when dealing
with early Virtex-4 revisions, altough it is not the case here).


I suggest to the OP that he should focus on verifying the obvious (pwr-supply levels,
input clock waveform, pin-mapping, UCF file, JTAG connection, DCM lock and status
outputs).

-- 
Matthieu Michon <p...@gmail.com>

If you are convinced that your simulation of the
design is correct then youreally need to use Chipscope to see what is going on inside the device. 

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

I am getting some warnings during post-par
simulation that may be a clue.When I load my routed design in Modelsim, I am getting 14 warnings likethis for different nets:

Instance 'top.fab.\fs1/ras/reset_n_inv_shift1 ' - No solution possible fordelayed timing check nets. Setting negative limit to zero.

In the static timing report for the OFFSET IN BEFORE timing constraint(which I have not set so it must be determined by ISE) I have a totalminimum clock path delay of -0.678 ns. 

For the OFFSET OUT AFTER constraint I have a maximum clock path delay of-0.256 ns. I wasn't sure if this meant something as the path for thesedelays are from the input clock buffer to the DCM. 

I don't believe the warnings in the simulation are normal but are negativedelay values normal?

Thanks,
Brandon


>If you are convinced that your simulation of the design is correct thenyou
>really need to use Chipscope to see what is going on inside the device. 
>
>Jon	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com