Hi,

I'm working with Xilinx ISE 10.1 and I am having troubles with timingconstraints.

I've successfully implemented my design with a 20 ns cycle time and foundthat I needed to change something in the design.

I make my changes and re-synthesize and implement design and I no longermeet the same timing constraint. Okay, I've changed the logic slightly soit's not going to be exactly the same, the static timing report says that Ineed a minimum cycle time of say 22 ns.

So I only change the timing constraint to reflect a 25 ns and re-run theprocess and it fails again saying I need a 32 ns cycle time now. Okay, so Ichange the cycle time to 35 ns and then I need a 46 ns cycle time.

I think this is understandable because with a relaxed constraint someoptimizations or paths may not be chosen. When do you try it again with thesame constraint and when do you relax the constraint? 

Thanks,
Brandon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Jun 10, 8:49=A0pm, "BrandonD"
<BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
> I make my changes and re-synthesize and implement design and I no longer
> meet the same timing constraint. Okay, I've changed the logic slightly so
> it's not going to be exactly the same, the static timing report says that=
 I
> need a minimum cycle time of say 22 ns.
>
> So I only change the timing constraint to reflect a 25 ns and re-run the
> process and it fails again saying I need a 32 ns cycle time now. Okay, so=
 I
> change the cycle time to 35 ns and then I need a 46 ns cycle time.
>
> I think this is understandable because with a relaxed constraint some
> optimizations or paths may not be chosen. When do you try it again with t=
he
> same constraint and when do you relax the constraint?

Actually, that doesn't make sense to me since the timing constraints
are supposed to be used in routing.  From what I have seen, synthesis,
such as Synplify, is often driven by a variety of specs, but not
necessarily the "constraints" that Xilinx lets you input.  Under the
Lattice tools I have to enter a separate timing constraint to have it
sent to Synplify when I use the GUI.  Even this is just one master
clock speed and so can't have the detail to constrain the paths that
have to be fast and relax the paths that don't need to run at full
speed.  There are also settings for "optimize for speed" or "optimize
for power".

I can't imagine what is going on that a path or paths can be de-
optimized repeatedly to always be just out of reach of your timing
constraint.  Have you looked at the paths to see if it is the same
path each time?  If path A fails with a 20 ns constraint and path B
fails with a 25 ns constraint what is path B doing under the 20 ns
constraint?  How does the tool make it meet 20 ns (or maybe just under
22 ns) and be slower otherwise?  Repeat with path C under the 35 ns,
etc.  See if you can figure out what is changing in the result.  There
has to be something odd going on.

Rick

On 6/11/2010 1:49 AM, BrandonD wrote:
> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
Hi Brandon,
It strikes me that if you are using a modern FPGA and can't meet a 20ns 
timing constraint, you have bigger problems than Xilinx's crappy software.
However, there are folks here who are queuing up to help. Tell us which 
device you are using and a bit about the portion of your design which 
fails timing.
Once that rafter is out of the way, we can look at the straws.
Cheers, Syms.

"BrandonD"
<BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes:

> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
> I make my changes and re-synthesize and implement design and I no longer
> meet the same timing constraint. Okay, I've changed the logic slightly so
> it's not going to be exactly the same, the static timing report says that I
> need a minimum cycle time of say 22 ns.
>
> So I only change the timing constraint to reflect a 25 ns and re-run the
> process and it fails again saying I need a 32 ns cycle time now. Okay, so I
> change the cycle time to 35 ns and then I need a 46 ns cycle time.
>
> I think this is understandable because with a relaxed constraint some
> optimizations or paths may not be chosen. When do you try it again with the
> same constraint and when do you relax the constraint? 

That looks quite weird.

BUT - I'm a bit confused -why would you relax the constraint?  

You set your constraint to match the physical system you are
targetting. Unless you can change that system to match your new
constraint, you can't just go changing constraints - are you planning
to slow your clock down as well?  Or have you overconstrained the
design?

Cheers,
Martin

-- 
m...@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Answering "Is it possible to get consistent
implementation results?".

Yes, if your constraints are set up properly you should get reliable
expected performance _every_ time you build the device (as long as
the constraits are met).


Nial. 

Thanks for the replies. 

As for the design, it is a superscalar processor not designed with FPGA inmind. Currently, I'm just trying to get it running on a Virtex-5 and Idon't care how slow it is. So yes, I am slowing the clock down as well.Actually, how I was changing the constraints was by changing the frequencyof the clock from the DCM and letting Xilinx detect the constraint for theclock. The clock into the FPGA and constraints for it have remained thesame. I'll work on speeding it up later. 

Without changing the design except the clock period and having nearly alloptimizations on and timing performance design strategy along with normalextra effort on map and par, I still couldn't meet a cycle time of 40 ns.Then I only changed the extra effort on map and par from normal to the nexthighest - continue on impossible - and it met a 30 ns cycle time. Xilinxeven mentions in the report that "continue on impossible" should not beneeded in normal cases.

I would really like to not have to use "continue on impossible" as it takesnearly 3 hours just for par. I'm using Xilinx 10.1 so no multi-threading.	  
					
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Posted through http://www.FPGARelated.com

You are doing something seriously wrong if it
takes 3 hours to p&r. Youneed to specify the clock that you want to run the design and then aftersynthesis examine the report to see if it has been met. If it hasnt thenyou need to investigate the paths that are failing and then modify thedesign to make it pass.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

I've specified the constraint on the clock to the
FPGA. That clock goes toa DCM and Xilinx generates a constraint for the output clock of the DCM. 

Synthesis runs fine, I get around a 3 ns cycle time. 

I don't get an error about failing timing constraints until after place androute has completed. I guess I just need to experiment to find out whatworks.

>You are doing something seriously wrong if it takes 3 hours to p&r. You
>need to specify the clock that you want to run the design and then after
>synthesis examine the report to see if it has been met. If it hasnt then
>you need to investigate the paths that are failing and then modify the
>design to make it pass.
>
>Jon	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>Hi,
>
>I'm working with Xilinx ISE 10.1 and I am having troubles with timing
>constraints.
>
>					
>---------------------------------------		
>


What is your % of utilization? Is this chip packed to the max?


Have you tried sacrificing a chicken on top of your workstation?


John 	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On 6/11/2010 4:52 PM, BrandonD wrote:
> Thanks for the replies.
>
> As for the design, it is a superscalar processor not designed with FPGA in
> mind.

Hi Brandon,

Wow, you are designing a "superscalar processor" and yet you can't meet 
FPGA timing?

Good luck with that!

Syms.