Help !!!   The megawizard in Quartus 2 does not
seem to support generating 
small roms & rams using the LUT
tables, only using the M9K memory blocks.  Any way to generate small roms & 
rams using the logic cells ?
I'm looking for something similar to Xilinx distributed memory generator. 
TIA.

Jim 

newzhnd <n...@home.com> wrote:

> Help !!!   The megawizard in Quartus 2 does not seem to support generating 
> small roms & rams using the LUT
> tables, only using the M9K memory blocks.  Any way to generate small roms & 
> rams using the logic cells ?
> I'm looking for something similar to Xilinx distributed memory generator. 
> TIA.

Can't you just generate them in ordinary verilog or VHDL?

For Xilinx, the RAM arrays are synchronous, so it has to generate
LUT RAM (or ROM) if it is used asynchronously.

-- glen

I'd rather not write verilog & specify each
rom or ram word individually. 
Cyclone 2 supports logic cell usage
for rom or ram. I'm surprised cyclone 3 doesn't.  Xilinx allows either LUT 
or block memory for ram or rom.
Nothing to do with sync or async.

"glen herrmannsfeldt" <g...@ugcs.caltech.edu> wrote in message 
news:hv3rmb$ul3$1...@speranza.aioe.org...
> newzhnd <n...@home.com> wrote:
>
>> Help !!!   The megawizard in Quartus 2 does not seem to support 
>> generating
>> small roms & rams using the LUT
>> tables, only using the M9K memory blocks.  Any way to generate small roms 
>> &
>> rams using the logic cells ?
>> I'm looking for something similar to Xilinx distributed memory generator.
>> TIA.
>
> Can't you just generate them in ordinary verilog or VHDL?
>
> For Xilinx, the RAM arrays are synchronous, so it has to generate
> LUT RAM (or ROM) if it is used asynchronously.
>
> -- glen 

"newzhnd" <n...@home.com> wrote
in message news:XaeRn.26714$%u...@newsfe14.iad...
> Help !!!   The megawizard in Quartus 2 does not seem to support generating small roms
& rams using 
> the LUT
> tables, only using the M9K memory blocks.  Any way to generate small roms & rams
using the logic 
> cells ?
> I'm looking for something similar to Xilinx distributed memory generator.


Altera devices can't implement LUT based distributed memory, this is one of
Xilinx's heavily patented uniqe selling points!

You just have to use device logic or M9Ks.


Nial. 

On Jun 14, 8:06=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> "newzhnd" <nob...@home.com> wrote in
messagenews:XaeRn.26714$%u7.16071@ne=
wsfe14.iad...
> > Help !!! =A0 The megawizard in Quartus 2 does not seem to support gener=
ating small roms & rams using
> > the LUT
> > tables, only using the M9K memory blocks. =A0Any way to generate small =
roms & rams using the logic
> > cells ?
> > I'm looking for something similar to Xilinx distributed memory generato=
r.
>
> Altera devices can't implement LUT based distributed memory, this is one =
of
> Xilinx's heavily patented uniqe selling points!
>
> You just have to use device logic or M9Ks.
>
> Nial.

If it's so heavily patented, why do Lattice devices support
distributed RAM?  There must be some work-arounds to the
existing patents.

> > Altera devices can't implement LUT
based distributed memory, this is one of
> > Xilinx's heavily patented uniqe selling points!

> If it's so heavily patented, why do Lattice devices support
> distributed RAM?  There must be some work-arounds to the
> existing patents.

Licensing?

It's a useful feature so I presumed (and have read here I think) the thing
stopping the other vendors implementing it is patents.


Nial.

On Mon, 14 Jun 2010 13:06:44 +0100, Nial Stewart
wrote:

> "newzhnd" <n...@home.com> wrote in message
> news:XaeRn.26714$%u...@newsfe14.iad...
>> Help !!!   The megawizard in Quartus 2 does not seem to support
>> generating small roms & rams using the LUT
>> tables, only using the M9K memory blocks.  Any way to generate small
>> roms & rams using the logic cells ?
>> I'm looking for something similar to Xilinx distributed memory
>> generator.
> 
> 
> Altera devices can't implement LUT based distributed memory, this is one
> of Xilinx's heavily patented uniqe selling points!
> 
> You just have to use device logic or M9Ks.
> 
> 
> Nial.

They can implement ROMs with LUTs, all logic in a LUT based FPGA is a 
ROM. The LUT RAM patent was filed in 1989 and granted in 1994 so it 
should expire next year, the patent term was 17 years from the date of 
grant in the early 90s.

On Jun 14, 3:25=A0pm, Gabor
<ga...@alacron.com> wrote:
> On Jun 14, 8:06=A0am, "Nial Stewart"
>
> <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > "newzhnd" <nob...@home.com> wrote in
messagenews:XaeRn.26714$%u7.16071@=
newsfe14.iad...
> > > Help !!! =A0 The megawizard in Quartus 2 does not seem to support gen=
erating small roms & rams using
> > > the LUT
> > > tables, only using the M9K memory blocks. =A0Any way to generate smal=
l roms & rams using the logic
> > > cells ?
> > > I'm looking for something similar to Xilinx distributed memory genera=
tor.
>
> > Altera devices can't implement LUT based distributed memory, this is on=
e of
> > Xilinx's heavily patented uniqe selling points!
>
> > You just have to use device logic or M9Ks.
>
> > Nial.
>
> If it's so heavily patented, why do Lattice devices support
> distributed RAM? =A0There must be some work-arounds to the
> existing patents.

very simple: Lattice has the license!
because AT&T used to to manufacture Xilinx compatible FPGA's
and Lattice is the current license holder of those old technologies
hence Lattice inherited the rights to use LUT as distributed RAM.

Other FPGA vendors like Altera can not do it without legal issues

Antti

"newzhnd" <n...@home.com> wrote in message 
news:JxeRn.38054$r...@newsfe10.iad...
> I'd rather not write verilog & specify each rom or ram word individually. 
> Cyclone 2 supports logic cell usage
> for rom or ram. I'm surprised cyclone 3 doesn't.  Xilinx allows either LUT 
> or block memory for ram or rom.
> Nothing to do with sync or async.
>
> "glen herrmannsfeldt" <g...@ugcs.caltech.edu> wrote in message 
> news:hv3rmb$ul3$1...@speranza.aioe.org...
>> newzhnd <n...@home.com> wrote:
>>
>>> Help !!!   The megawizard in Quartus 2 does not seem to support 
>>> generating
>>> small roms & rams using the LUT
>>> tables, only using the M9K memory blocks.  Any way to generate small 
>>> roms &
>>> rams using the logic cells ?
>>> I'm looking for something similar to Xilinx distributed memory 
>>> generator.
>>> TIA.
>>
>> Can't you just generate them in ordinary verilog or VHDL?
>>
>> For Xilinx, the RAM arrays are synchronous, so it has to generate
>> LUT RAM (or ROM) if it is used asynchronously.
>>
>> -- glen
>
>


Just use the LPM_CONSTANT primitive and specify the bit width and value. I
am sure you can take it from there ....

On Jun 14, 2:06=A0pm, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> "newzhnd" <nob...@home.com> wrote in
messagenews:XaeRn.26714$%u7.16071@ne=
wsfe14.iad...
> > Help !!! =A0 The megawizard in Quartus 2 does not seem to support gener=
ating small roms & rams using
> > the LUT
> > tables, only using the M9K memory blocks. =A0Any way to generate small =
roms & rams using the logic
> > cells ?
> > I'm looking for something similar to Xilinx distributed memory generato=
r.
>
> Altera devices can't implement LUT based distributed memory, this is one =
of
> Xilinx's heavily patented uniqe selling points!
>

In fact Stratix3/4 and Aria2 support MLAB which is very similar to
Xilinx distributed memory. So obviously they found a hole in Xilinx
patent.

> You just have to use device logic or M9Ks.

For RAM on C2 - yes. Except, it's M4K rather than M9K
As already mentioned here, even on C2 synthesis tools should be able
to implement small ROM in LUTs.
However, AFAIR,  Quartus-II does not support initializing of such ROM
from .mif or .hex file so every change of the ROM contest would
require full recompilation.

>
> Nial.