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Comp.Arch.FPGA | Power Management for PCIe

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Power Management for PCIe - Usama - 2010-06-14 03:04:00

hi

I am implementing BMD design as explained in xapp1052(v2.5). Have
implemented the design on Avnet V5LXT/SXT PCIe Development Board using
the PCIe. Have generated the Endpoint Block plus for PCIe 1.9 using
ISE 10.1. I have been successful in running the BMD design. I want to
switch off the power management at the system start up.

in my understanding there can be two ways to do it. firstly through
the bios setting and other at the time of core generation.


i am working on the bios part but i want to know about the power
management option present at the time of core generation. What would
be the result if i use that option. will that option help me in
switching off the power management.



Secondly is there any option in the RTL of XAPP1052 which could be
hard coded to stop the power management negotiation at the system
startup?
Can i set any options at the time time of bit stream generation that
would help me in switching off the power management.

Regards

Usama
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