Hello.

I am working at an SoC startup developing EDA software for FPGA-like
structures. Currently we have a half-finished software covering from
technology mapping to placement and routing for FPGA. I am looking for
opportunities to put the software into practice.

Originally the software was expected to evaluate FPGA structures
(known or unknown) for various application domains. So it is not
designated to any specific logic cell or interconnect. Instead, given
structure descriptions, this software can perform technology mapping,
packing, placement and routing on a wide variety of
structures. Actually, there does exist limitations like entities in
logic cell must be organized in tree structure, interconnection must
build on switches and the overall structure must be repetitive. Even
though, the software is flexible enough to be customized to different
FPGA structures.

The frustration I am facing to is that there is few chance to practice
since the top priority task for a startup is to make money and
survive. So after talking with my boss, now I am seeking opportunities
outside.

Main features of the software:

  1. Flexible logic cell structure. We have developed algorithm
  performing technology mapping and packing in the same time. The
  logic cell don't need to be look-up table only. You can add in other
  special purpose entities like mux. The software can automatically
  map and pack netlist into expected logic cells given a proper
  specification.

  2. Flexible interconnection. Similiar to VPR, the placement and
  routing algorithms work on abstract interconnection model.

  3. Heterogeneous placement. What VPR cannot do is placement for
  blocks of different size, which is an unavoidable case for
  real-world FPGA designs. For example, adders are usually synthesized
  to a bank of logic cells which requires to be placed along dedicated
  carry chains. Our algorithm deals with such cases by a
  partition-and-place approach.

  4. Unified design representation. All algorithms read design from
  and store to the same database. So there is no need for data
  transformation as using discrete tools like ABCmap and VPR.

  5. Complete Pythonization (ongoing). The database and core
  algorithms are written in C++. But we are porting the database to
  Python so that one can operate on designs directly from Python. The
  core algorithms will also be exposed to Python. By enjoying the
  elegancy and extensibility of Python, design flows are built up
  quite easily.

Then I have to mention some shortages of the software.

  1. No GUI/IDE. We are used to scripting and is unfamiliar with
  GUI development. But I think with Python it is easy to design
  cross-platform GUI and IDE.

  2. No RTL design entry. Currently we are using icarus to parse RTL
  Verilog to gate level. We are thinking of build an RTL HDL parser
  but haven't have time to kick it off.

  3. No synthesis optimization. Since we haven't reach RTL level,
  there is no synthesis and logic optimization algorithms yet.

  4. Not timing-driven. Existing algorithms are bound to resource
  constraints. We haven't put timing constraints into consideration
  yet.

I am wondering whether there is any FPGA startup or other design house
that works on embedded reconfigurable fabric will need such kind of
software. If not any, it will be locked up in the basement until 2012
or someday due to the company strategy. As a main developer, I will be
very sad if so. That is why I post here. I am looking for an
opportunity to practice and to push forward the software.

Personally I think open-source is one of the possible way out and it
is the most interesting way. It will be cool if we can build up an
open source design automation flow to lower the software barrel for
FPGA/reconfigurable market. But there is a long way to go. Besides,
since the software is still my company's proprietary, though the
company is open to open source, I have to find a profitable reason for
open-source.

Should you have any suggestions, advices, critism or willings, please
fill free to let me know. I will appreciate very much for your feed
back. And thank you for reading this far.

Yujie Wen

Celestial Semiconductor.
Shanghai Office.
yujie.wen REPLACE_WITH_AT celestialsemi.cn




	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>Hello.
>
>I am working at an SoC startup developing EDA software for FPGA-like
>structures. Currently we have a half-finished software covering from
>technology mapping to placement and routing for FPGA. I am looking for
>opportunities to put the software into practice.
>
>Originally the software was expected to evaluate FPGA structures
>(known or unknown) for various application domains. So it is not
>designated to any specific logic cell or interconnect. Instead, given
>structure descriptions, this software can perform technology mapping,
>packing, placement and routing on a wide variety of
>structures. Actually, there does exist limitations like entities in
>logic cell must be organized in tree structure, interconnection must
>build on switches and the overall structure must be repetitive. Even
>though, the software is flexible enough to be customized to different
>FPGA structures.
>
>The frustration I am facing to is that there is few chance to practice
>since the top priority task for a startup is to make money and
>survive. So after talking with my boss, now I am seeking opportunities
>outside.
>
>Main features of the software:
>
>  1. Flexible logic cell structure. We have developed algorithm
>  performing technology mapping and packing in the same time. The
>  logic cell don't need to be look-up table only. You can add in other
>  special purpose entities like mux. The software can automatically
>  map and pack netlist into expected logic cells given a proper
>  specification.
>
>  2. Flexible interconnection. Similiar to VPR, the placement and
>  routing algorithms work on abstract interconnection model.
>
>  3. Heterogeneous placement. What VPR cannot do is placement for
>  blocks of different size, which is an unavoidable case for
>  real-world FPGA designs. For example, adders are usually synthesized
>  to a bank of logic cells which requires to be placed along dedicated
>  carry chains. Our algorithm deals with such cases by a
>  partition-and-place approach.
>
>  4. Unified design representation. All algorithms read design from
>  and store to the same database. So there is no need for data
>  transformation as using discrete tools like ABCmap and VPR.
>
>  5. Complete Pythonization (ongoing). The database and core
>  algorithms are written in C++. But we are porting the database to
>  Python so that one can operate on designs directly from Python. The
>  core algorithms will also be exposed to Python. By enjoying the
>  elegancy and extensibility of Python, design flows are built up
>  quite easily.
>
>Then I have to mention some shortages of the software.
>
>  1. No GUI/IDE. We are used to scripting and is unfamiliar with
>  GUI development. But I think with Python it is easy to design
>  cross-platform GUI and IDE.
>
>  2. No RTL design entry. Currently we are using icarus to parse RTL
>  Verilog to gate level. We are thinking of build an RTL HDL parser
>  but haven't have time to kick it off.
>
>  3. No synthesis optimization. Since we haven't reach RTL level,
>  there is no synthesis and logic optimization algorithms yet.
>
>  4. Not timing-driven. Existing algorithms are bound to resource
>  constraints. We haven't put timing constraints into consideration
>  yet.
>
>I am wondering whether there is any FPGA startup or other design house
>that works on embedded reconfigurable fabric will need such kind of
>software. If not any, it will be locked up in the basement until 2012
>or someday due to the company strategy. As a main developer, I will be
>very sad if so. That is why I post here. I am looking for an
>opportunity to practice and to push forward the software.
>
>Personally I think open-source is one of the possible way out and it
>is the most interesting way. It will be cool if we can build up an
>open source design automation flow to lower the software barrel for
>FPGA/reconfigurable market. But there is a long way to go. Besides,
>since the software is still my company's proprietary, though the
>company is open to open source, I have to find a profitable reason for
>open-source.
>
>Should you have any suggestions, advices, critism or willings, please
>fill free to let me know. I will appreciate very much for your feed
>back. And thank you for reading this far.
>
>Yujie Wen
>
>Celestial Semiconductor.
>Shanghai Office.
>yujie.wen REPLACE_WITH_AT celestialsemi.cn
>
>
>
>
>	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>

For your HDL entry and parsing - why don't you use MyHDL ? It is a pythonmodule so would gel with your pythonization idea. It also has a built inverilod/vhdl code generator.

Personally I would love to contribute to an open source fpga developmenttool. So if it is going to be locked up, its better to release it as opensource; the making money part can come later when the software picks up.	  
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>>Hello.
>>
>>I am working at an SoC startup developing EDA software for FPGA-like
>>structures. Currently we have a half-finished software covering from
>>technology mapping to placement and routing for FPGA. I am looking for
>>opportunities to put the software into practice.
>>
>>Originally the software was expected to evaluate FPGA structures
>>(known or unknown) for various application domains. So it is not
>>designated to any specific logic cell or interconnect. Instead, given
>>structure descriptions, this software can perform technology mapping,
>>packing, placement and routing on a wide variety of
>>structures. Actually, there does exist limitations like entities in
>>logic cell must be organized in tree structure, interconnection must
>>build on switches and the overall structure must be repetitive. Even
>>though, the software is flexible enough to be customized to different
>>FPGA structures.
>>
>>The frustration I am facing to is that there is few chance to practice
>>since the top priority task for a startup is to make money and
>>survive. So after talking with my boss, now I am seeking opportunities
>>outside.
>>
>>Main features of the software:
>>
>>  1. Flexible logic cell structure. We have developed algorithm
>>  performing technology mapping and packing in the same time. The
>>  logic cell don't need to be look-up table only. You can add in other
>>  special purpose entities like mux. The software can automatically
>>  map and pack netlist into expected logic cells given a proper
>>  specification.
>>
>>  2. Flexible interconnection. Similiar to VPR, the placement and
>>  routing algorithms work on abstract interconnection model.
>>
>>  3. Heterogeneous placement. What VPR cannot do is placement for
>>  blocks of different size, which is an unavoidable case for
>>  real-world FPGA designs. For example, adders are usually synthesized
>>  to a bank of logic cells which requires to be placed along dedicated
>>  carry chains. Our algorithm deals with such cases by a
>>  partition-and-place approach.
>>
>>  4. Unified design representation. All algorithms read design from
>>  and store to the same database. So there is no need for data
>>  transformation as using discrete tools like ABCmap and VPR.
>>
>>  5. Complete Pythonization (ongoing). The database and core
>>  algorithms are written in C++. But we are porting the database to
>>  Python so that one can operate on designs directly from Python. The
>>  core algorithms will also be exposed to Python. By enjoying the
>>  elegancy and extensibility of Python, design flows are built up
>>  quite easily.
>>
>>Then I have to mention some shortages of the software.
>>
>>  1. No GUI/IDE. We are used to scripting and is unfamiliar with
>>  GUI development. But I think with Python it is easy to design
>>  cross-platform GUI and IDE.
>>
>>  2. No RTL design entry. Currently we are using icarus to parse RTL
>>  Verilog to gate level. We are thinking of build an RTL HDL parser
>>  but haven't have time to kick it off.
>>
>>  3. No synthesis optimization. Since we haven't reach RTL level,
>>  there is no synthesis and logic optimization algorithms yet.
>>
>>  4. Not timing-driven. Existing algorithms are bound to resource
>>  constraints. We haven't put timing constraints into consideration
>>  yet.
>>
>>I am wondering whether there is any FPGA startup or other design house
>>that works on embedded reconfigurable fabric will need such kind of
>>software. If not any, it will be locked up in the basement until 2012
>>or someday due to the company strategy. As a main developer, I will be
>>very sad if so. That is why I post here. I am looking for an
>>opportunity to practice and to push forward the software.
>>
>>Personally I think open-source is one of the possible way out and it
>>is the most interesting way. It will be cool if we can build up an
>>open source design automation flow to lower the software barrel for
>>FPGA/reconfigurable market. But there is a long way to go. Besides,
>>since the software is still my company's proprietary, though the
>>company is open to open source, I have to find a profitable reason for
>>open-source.
>>
>>Should you have any suggestions, advices, critism or willings, please
>>fill free to let me know. I will appreciate very much for your feed
>>back. And thank you for reading this far.
>>
>>Yujie Wen
>>
>>Celestial Semiconductor.
>>Shanghai Office.
>>yujie.wen REPLACE_WITH_AT celestialsemi.cn
>>
>>
>>
>>
>>	   
>>					
>>---------------------------------------		
>>Posted through http://www.FPGARelated.com
>>
>
>For your HDL entry and parsing - why don't you use MyHDL ? It is a python
>module so would gel with your pythonization idea. It also has a built in
>verilod/vhdl code generator.

We can't force designers give up Verilog or VHDL and rewrite their design
in MyHDL. I am afraid the software will never be popular without support 
to popular HDL entries. But MyHDL is a great plus. And I will work out a
MyHDL entry later because, as you said, Python is the easy-to-go bridge 
between the two.

>
>Personally I would love to contribute to an open source fpga development
>tool. So if it is going to be locked up, its better to release it as open
>source; the making money part can come later when the software picks up.	 

That's great! Let me first find a win-win solution towards open-source. :)

>
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>

Yujie	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com