Hi all,
 I'm developping a firmware using Xilinx FPGA spartan3, I want to use
an FPGA core which has the same functionality as altshift in Altera
FPGA, I was thinking about using FIFO but  I need to implement 4 taps.
Anyone knows well about Altera and Xilinx could help me please? Thank
you !!

Gladys <y...@gmail.com> wrote:
> Hi all,
>  I'm developping a firmware using Xilinx FPGA spartan3, I want to use
> an FPGA core which has the same functionality as altshift in Altera
> FPGA, I was thinking about using FIFO but  I need to implement 4 taps.
> Anyone knows well about Altera and Xilinx could help me please? Thank
> you !!

What is "altshift"?
-- 
Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On 23 juin, 13:33, Uwe Bonnes
<b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Gladys <yuhu...@gmail.com> wrote:
> > Hi all,
> > =A0I'm developping a firmware using Xilinx FPGA spartan3, I want to use
> > an FPGA core which has the same functionality as altshift in Altera
> > FPGA, I was thinking about using FIFO but =A0I need to implement 4 taps=
.
> > Anyone knows well about Altera and Xilinx could help me please? Thank
> > you !!
>
> What is "altshift"?
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


altshift_taps: It's a megafuncthin provided by Altera FPGA, here is
the user manual http://www.altera.com/literature/ug/ug_shift_register_ram_b=
ased.pdf
 It's a RAM base shiftregister, actually I want to do image processing
while receiving the real time pixel data, the image resolution is
1028H * 1024L and FPGA receives the data line by line, but I need a 5H
x 5L real time image data so I want to know how could I realize it.

I found that Xilinx provide an IP core called
RAM-based Shift
Register, the maximum depth is 1088, however, my image could have a
high resolution of 3664 x 2748, which means I need a depth of 2748, is
there any other methode to implement this? Thank you

On Jun 23, 7:54=A0am, Gladys
<yuhu...@gmail.com> wrote:
> I found that Xilinx provide an IP core called RAM-based Shift
> Register, the maximum depth is 1088, however, my image could have a
> high resolution of 3664 x 2748, which means I need a depth of 2748, is
> there any other methode to implement this? Thank you

There's a white paper from Xilinx titled "Implementing and Testing
Efficient Video Line Stores". It explains how to use Block RAMs as a
huge shift register of an arbitrary length. I've used the provided
examples with success in the past. You can find it here:
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

Regards,
Sergio

Sergio <c...@gmail.com> wrote:

>On Jun 23, 7:54=A0am, Gladys <yuhu...@gmail.com> wrote:
>> I found that Xilinx provide an IP core called RAM-based Shift
>> Register, the maximum depth is 1088, however, my image could have a
>> high resolution of 3664 x 2748, which means I need a depth of 2748, is
>> there any other methode to implement this? Thank you
>
>There's a white paper from Xilinx titled "Implementing and Testing
>Efficient Video Line Stores". It explains how to use Block RAMs as a
>huge shift register of an arbitrary length. I've used the provided
>examples with success in the past. You can find it here:
>http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

Such designs are actually circular buffers. Not very difficult to
create by yourself.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On 23 juin, 19:50, Sergio
<chec...@gmail.com> wrote:
> On Jun 23, 7:54=A0am, Gladys <yuhu...@gmail.com> wrote:
>
> > I found that Xilinx provide an IP core called RAM-based Shift
> > Register, the maximum depth is 1088, however, my image could have a
> > high resolution of 3664 x 2748, which means I need a depth of 2748, is
> > there any other methode to implement this? Thank you
>
> There's a white paper from Xilinx titled "Implementing and Testing
> Efficient Video Line Stores". It explains how to use Block RAMs as a
> huge shift register of an arbitrary length. I've used the provided
> examples with success in the past. You can find it here:http://www.xilinx=
.com/products/boards/s3estarter/reference_designs.htm
>
> Regards,
> Sergio

On 23 juin, 19:50, Sergio <chec...@gmail.com> wrote:
> On Jun 23, 7:54 am, Gladys <yuhu...@gmail.com> wrote:
>
> > I found that Xilinx provide an IP core called RAM-based Shift
> > Register, the maximum depth is 1088, however, my image could have a
> > high resolution of 3664 x 2748, which means I need a depth of 2748, is
> > there any other methode to implement this? Thank you
>
> There's a white paper from Xilinx titled "Implementing and Testing
> Efficient Video Line Stores". It explains how to use Block RAMs as a
> huge shift register of an arbitrary length. I've used the provided
> examples with success in the past. You can find it here:http://www.xilinx=
.com/products/boards/s3estarter/reference_designs.htm
>
> Regards,
> Sergio

Thank you so much for help, I've successfully implemented the line
buffer of about 3000 delay of data 12bits for my image processing.
Now I have another question: the pixels are in bayer pattern, such as:

          R1
      B  G  B
R2  G  R  G  R3
      B  G  B
          R4

I want to correct the defective pixel 5x5 pixel surrounding, then
replace it by the average value of the nearest same color neighbor
pixels.
For example, the R in the middle is a dead pixel, then R=3D(R1+R2+R3+R4)/
4

In vertical, I've built 4 line buffer, but in horizontal, I still need
to have 5 pixels available at the same time, do I need to use shift
registers again to
delay the data for 4, 3, 2, 1clock cycle?

I find it's memory consuming and I'm not sure if my solution is
correct.  Could you please help me? Thanks again.

Gladys <y...@gmail.com> writes:

> Thank you so much for help, I've successfully implemented the line
> buffer of about 3000 delay of data 12bits for my image processing.
> Now I have another question: the pixels are in bayer pattern, such as:
>
>           R1
>       B  G  B
> R2  G  R  G  R3
>       B  G  B
>           R4
>
> I want to correct the defective pixel 5x5 pixel surrounding, then
> replace it by the average value of the nearest same color neighbor
> pixels.
> For example, the R in the middle is a dead pixel, then R=(R1+R2+R3+R4)/
> 4
>
> In vertical, I've built 4 line buffer, but in horizontal, I still need
> to have 5 pixels available at the same time, do I need to use shift
> registers again to
> delay the data for 4, 3, 2, 1clock cycle?

Single tick delays are just flip-flops, so you'll need 4 sets of 12
bits => 48 flipflops.

>
> I find it's memory consuming and I'm not sure if my solution is
> correct.  Could you please help me? Thanks again.

Which bit is memory consuming?  Not the horizontal buffers I hope!

The vertical line buffers will need as many elements as you have
pixels to store (4 complete lines).  There's not a lot you can do
about this - if you need to look back by 4 lines, you need to store 4
lines to do it.

Cheers,
Martin

-- 
m...@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html