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Comp.Arch.FPGA | help with OVL on Actel tool
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help with OVL on Actel tool - tullio - 2010-06-28 08:20:00
Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but in the Actel Libero tool I can't find any way to add a path to the library. So if on my verilog code I put a OVL assertion, it will be flagged as an error by the Actel "Check HDL file" feature. Any advice ?______________________________
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Re: help with OVL on Actel tool - d_s_klein - 2010-06-28 18:46:00
On Jun 28, 5:20=A0am, tullio <tullio.gra...@gmail.com> wrote: > Hi, > > =A0I am a verilog designer and I'd like to try OVL on an Actel design. > I can't figure out how to use the OVL library. > I downloaded it, but in the Actel Libero tool I can't find any way to > add a path to the library. > So if on my verilog code I put a OVL assertion, it will be flagged as > an error by the Actel "Check HDL file" feature. > Any advice ? What makes you think that the Actel synthesizer is going to be able to deal with the Open Verification Library? AKAIK, there are few to no synthesizable parts of that library. RK