Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST


Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | error in XPS

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

error in XPS - ravihma - 2010-06-29 14:38:00

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'mult_ipif_0/mult_ipif_0/USER_LOGIC_I'with
   type 'user_logic' could not be resolved. A pin name misspelling cancause
   this, a missing edif or ngc file, or the misspelling of a type name.Symbol
   'user_logic' is not supported in target 'spartan3e'.
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clockdriver
   debug_module/debug_module/BUFG_DRCK1 drives no clock pins

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   1


One or more errors were found during NGDBUILD.  No NGD file will bewritten.

Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flowexecution...
    
make: *** [__xps/system_routed] Error 1
Done!
can any one help ? i am learning this tool for EDk

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com