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Comp.Arch.FPGA | SPI Flash configuration and data access rate

There are 6 messages in this thread.

You are currently looking at messages 0 to 6.

SPI Flash configuration and data access rate - Gladys - 2010-07-02 05:30:00

Hi, I'm implementing an FPGA prototype to do some
image processing
such as dead pixel correction. The xilinx FPGA will be configured with
an SPI flash memory,where the .bit configuration file inside as well
as dead pixel locations are stored.

I want to correct the dead pixel while receiving each pixel data,
compare each location with the pre-stored dead pixel locations, if it
turns out to be a dead pixel, I can directly correct it.

The question are:
1How could I access the locations information? should I first read
them out and store in the dualport SDRAM?
2How can I know if the current pixel location equals to one of  the
dead pixel locations? What I can do is to compare current location to
all the locations one by one, however, if there are 100 bad pixel
location, and my input pixel data rate is 25MHZ, I need to have pixel
location data rate of 25MHZ * 100 to make sure I can compare them all
while receiving one pixel data. This is impossibel.

Thanksfor your helps!



Re: SPI Flash configuration and data access rate - Gladys - 2010-07-02 05:39:00

Sorry, for the 2nd question, I just forgot that I
can use Lool Up
Table, just use CASE statement to implement this.
So the only problem is how can I access the location data from SPI
flash, since these data should be always available for bad pixel
correction while FPGA running.

Re: SPI Flash configuration and data access rate - glen herrmannsfeldt - 2010-07-02 08:35:00

Gladys <y...@gmail.com> wrote:

> Hi, I'm implementing an FPGA prototype to do some image processing
> such as dead pixel correction. The xilinx FPGA will be configured with
> an SPI flash memory,where the .bit configuration file inside as well
> as dead pixel locations are stored.
 
> I want to correct the dead pixel while receiving each pixel data,
> compare each location with the pre-stored dead pixel locations, if it
> turns out to be a dead pixel, I can directly correct it.
 
> The question are:
> 1How could I access the locations information? should I first read
> them out and store in the dualport SDRAM?

I would probably store inside the FPGA, either BRAM or LUT RAM.
There aren't so many dead pixels that it won't fit, right?

> 2How can I know if the current pixel location equals to one of  the
> dead pixel locations? What I can do is to compare current location to
> all the locations one by one, however, if there are 100 bad pixel
> location, and my input pixel data rate is 25MHZ, I need to have pixel
> location data rate of 25MHZ * 100 to make sure I can compare them all
> while receiving one pixel data. This is impossibel.

If they are in the right order, you always know which one is 
coming next.  Just compare one!

Though many FPGA are big enough to do the compares in parallel,
you would need to program in the maximum number such that enough
comparators were generated.

-- glen

Re: SPI Flash configuration and data access rate - John Larkin - 2010-07-02 17:58:00

On Fri, 2 Jul 2010 12:35:20 +0000 (UTC), glen
herrmannsfeldt
<g...@ugcs.caltech.edu> wrote:

>Gladys <y...@gmail.com> wrote:
>
>> Hi, I'm implementing an FPGA prototype to do some image processing
>> such as dead pixel correction. The xilinx FPGA will be configured with
>> an SPI flash memory,where the .bit configuration file inside as well
>> as dead pixel locations are stored.
> 
>> I want to correct the dead pixel while receiving each pixel data,
>> compare each location with the pre-stored dead pixel locations, if it
>> turns out to be a dead pixel, I can directly correct it.
> 
>> The question are:
>> 1How could I access the locations information? should I first read
>> them out and store in the dualport SDRAM?
>
>I would probably store inside the FPGA, either BRAM or LUT RAM.
>There aren't so many dead pixels that it won't fit, right?
>
>> 2How can I know if the current pixel location equals to one of  the
>> dead pixel locations? What I can do is to compare current location to
>> all the locations one by one, however, if there are 100 bad pixel
>> location, and my input pixel data rate is 25MHZ, I need to have pixel
>> location data rate of 25MHZ * 100 to make sure I can compare them all
>> while receiving one pixel data. This is impossibel.
>
>If they are in the right order, you always know which one is 
>coming next.  Just compare one!
>
>Though many FPGA are big enough to do the compares in parallel,
>you would need to program in the maximum number such that enough
>comparators were generated.
>
>-- glen

Or use a block ram as a direct bad-pixel map, assuming you have as
many bits of ram available as pixels in the image.

At load time, a short (x,y) list of bad pixels could be read from
serial flash and use to set the tag bits in the ram.

John


Re: SPI Flash configuration and data access rate - glen herrmannsfeldt - 2010-07-02 18:07:00

John Larkin
<j...@highnotlandthistechnologypart.com> wrote:
(snip, I wrote)

>>I would probably store inside the FPGA, either BRAM or LUT RAM.
>>There aren't so many dead pixels that it won't fit, right?
(snip)
 
> Or use a block ram as a direct bad-pixel map, assuming you have as
> many bits of ram available as pixels in the image.

Yes you could do that.  As the number of pixels per display is
ever increasing, though, it might not be so convenient.
 
> At load time, a short (x,y) list of bad pixels could be read from
> serial flash and use to set the tag bits in the ram.

OK, so parallel load a word from BRAM, and shift it at the
pixel clock rate.  It might be that is faster than a comparator, 
though the comparator could be pipelined if needed, for speed.
The BRAM load would have to be carefully pipelined to arrive
at the appropriate time.

As far as I know, most set a low maximum for the number of
bad pixels.  I believe my monitor has none, though I might not
notice a black pixel.

-- glen

Re: SPI Flash configuration and data access rate - Martin Thompson - 2010-07-05 06:57:00

Gladys <y...@gmail.com> writes:

> Sorry, for the 2nd question, I just forgot that I can use Lool Up
> Table, just use CASE statement to implement this.
> So the only problem is how can I access the location data from SPI
> flash, since these data should be always available for bad pixel
> correction while FPGA running.

If you use a BRAM to store the data, you can arrange to have it
initialised by the bitstream, so you don't need to do that.  This
means a new bitstream for each set of bad pixels though, so that might
not work out in your application!

In which case, you need to write a small peripheral, or use a small
microcontroller core in the FPGA to read the data from the SPI flash
(once, at startup) into a BRAM internally.  Then you can use that data
to feed to your dead-pixel corrector.

Cheers,
Martin


-- 
m...@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
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