I'm trying to see the difference from an external
point of view, and I
can't see one, apart from having a 1.8V supply rather than a 2.5V.

I can see increased clock speed and increased clock latency, but
that's about it

I am aware the internal clock runs at half main clock, and that the
burst order in interleaved data is different, but on the surface I
should be able to use a DDR controller to access DDR2.  Where am I
going wrong?

I have used DDR2 but not DDR but I am fairly sure
that the init seq isdifferent. I wouldnt be surprised if there are different timings and bursttypes too. Because of the faster timings on DDR2 some form of readcalibration would be needed. So you could probably modify a DDR controllerbut using it straight out of the box is not possible.

Jon 	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On 5 July, 11:45, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I have used DDR2 but not DDR but I am fairly sure that the init seq is
> different. I wouldnt be surprised if there are different timings and burs=
t
> types too. Because of the faster timings on DDR2 some form of read
> calibration would be needed. So you could probably modify a DDR controlle=
r
> but using it straight out of the box is not possible.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

I have control over the initialisation sequence so that should not be
an issue. I also have control over the clock and strobe timings as
well.

You haven't outlined any show-stoppers that I might have expected.

Many thanks for your view.

On Jul 5, 8:21=A0am, Fred
<fred__blo...@lycos.com> wrote:
> On 5 July, 11:45, "maxascent"
>
> <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> > I have used DDR2 but not DDR but I am fairly sure that the init seq is
> > different. I wouldnt be surprised if there are different timings and bu=
rst
> > types too. Because of the faster timings on DDR2 some form of read
> > calibration would be needed. So you could probably modify a DDR control=
ler
> > but using it straight out of the box is not possible.
>
> > Jon =A0 =A0 =A0 =A0
>
> > --------------------------------------- =A0 =A0 =A0 =A0
> > Posted throughhttp://www.FPGARelated.com
>
> I have control over the initialisation sequence so that should not be
> an issue. I also have control over the clock and strobe timings as
> well.
>
> You haven't outlined any show-stoppers that I might have expected.
>
> Many thanks for your view.

I think you may be able to configure the DQS as single-ended, but
normally
DDR2 uses differential DQS signals.  Also on-die termination was added
in
DDR2, this requires an extra signal if you use it.  The start-up
sequences are
different and the DDR2 has more mode registers.

Regards,
Gabor

On 5 July, 20:53, Gabor <ga...@alacron.com>
wrote:
> On Jul 5, 8:21=A0am, Fred <fred__blo...@lycos.com> wrote:
>
>
>
>
>
> > On 5 July, 11:45, "maxascent"
>
> > <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> > > I have used DDR2 but not DDR but I am fairly sure that the init seq i=
s
> > > different. I wouldnt be surprised if there are different timings and =
burst
> > > types too. Because of the faster timings on DDR2 some form of read
> > > calibration would be needed. So you could probably modify a DDR contr=
oller
> > > but using it straight out of the box is not possible.
>
> > > Jon =A0 =A0 =A0 =A0
>
> > > --------------------------------------- =A0 =A0 =A0 =A0
> > > Posted throughhttp://www.FPGARelated.com
>
> > I have control over the initialisation sequence so that should not be
> > an issue. I also have control over the clock and strobe timings as
> > well.
>
> > You haven't outlined any show-stoppers that I might have expected.
>
> > Many thanks for your view.
>
> I think you may be able to configure the DQS as single-ended, but
> normally
> DDR2 uses differential DQS signals. =A0Also on-die termination was added
> in
> DDR2, this requires an extra signal if you use it. =A0The start-up
> sequences are
> different and the DDR2 has more mode registers.
>
> Regards,
> Gabor- Hide quoted text -
>

A Micron datasheet suggests that the DQS# need not be used where the
option has been chosen in the Mode Register, implying that single
ended strobe operation would be fine.

I have control over the start-up sequence so this should not be an
issue.

Given I only anticipate using a single rank of memory, I had hoped
that I could assert ODT once the extended mode register had been
written.  I don't anticipate using self-refresh which also requires
ODT to be pulled during refresh.

Many thanks.